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An Error Diagnosis Technique Based on Clustering of Elements Kosuke SHIOKI Narumi OKADA Kosuke WATANABE Tetsuya HIROSE Nobutaka KUROKI Masahiro NUMA Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E93-A No.12 pp.2490-2496 Publication Date: 2010/12/01 Online ISSN: 1745-1337 DOI: 10.1587/transfun.E93.A.2490 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: ECO, error diagnosis, incremental synthesis, LUT, Full Text: PDF(1.4MB)>>
Summary: In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique. | ||||||||||
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