IEICE Trans - 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

Shunsuke OKUMURA
Yuki KAGIYAMA
Yohei NAKATA
Shusuke YOSHIMOTO
Hiroshi KAWAGUCHI
Masahiko YOSHIMOTO

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E94-A No.12 pp.2693-2700
Publication Date: 2011/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E94.A.2693
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword:
SRAM DMA, transactional memory, checkpoint and recovery, multi-core processor,

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Summary:
This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.

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