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An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies Li DING Zhangcai HUANG Atsushi KUROKAWA Jing WANG Yasuaki INOUE Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E97-A No.5 pp.1059-1074 Publication Date: 2014/05/01 Online ISSN: 1745-1337 DOI: 10.1587/transfun.E97.A.1059 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: gate delay, overshooting effect, multiple-input gates, nanometer technology, Full Text: PDF(2.4MB)>>
Summary: With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model. | ||||||||||
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