Tunable Threshold Voltage of Organic CMOS Inverter Circuits by Electron Trapping in Bilayer Gate Dielectrics

Toan Thanh DAO
Hideyuki MURATA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E98-C    No.5    pp.422-428
Publication Date: 2015/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.422
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
controllable threshold voltage,  stretch-exponential equation,  noise margin enhancement,  organic CMOS inverter,  

Full Text: PDF(1.1MB)
Summary: 
We have demonstrated tunable n-channel fullerene and p-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO2. For both OFET types, the Vth can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO2. The stability of the shifted Vth was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 106 s. For organic CMOS inverter, after applying the program gate voltages for n-channel fullerene or p-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60 V for p-channel OFET, the circuit switched at 4, 8 V, that is close to half supply voltage VDD, leading to the maximum electrical noise immunity of the inverter circuit.