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ORCID8. Conference On Computing Frontiers 2011: Ischia, Italy
- Calin Cascaval, Pedro Trancoso, Viktor K. Prasanna:
Proceedings of the 8th Conference on Computing Frontiers, 2011, Ischia, Italy, May 3-5, 2011. ACM 2011, ISBN 978-1-4503-0698-0
Processor and memory architecture
- Abhishek Deb, Josep M. Codina, Antonio González
:
SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. 1 - Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik:
Efficient stack distance computation for priority replacement policies. 2 - Chunyang Gou, Georgi Gaydadjiev:
Elastic pipeline: addressing GPU on-chip shared memory bank conflicts. 3
Performance evaluation and programming model
- Rosario Cammarota, Arun Kejariwal, Paolo D'Alberto, Sapan Panigrahi, Alexander V. Veidenbaum, Alexandru Nicolau:
Pruning hardware evaluation space via correlation-driven application similarity analysis. 4 - Socrates Demetriades, Sangyeun Cho:
BarrierWatch: characterizing multithreaded workloads across and within program-defined epochs. 5 - Lingyuan Wang, Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Ghazawi:
Scaling scientific applications on clusters of hybrid multicore/GPU nodes. 6
Design for performance and resource efficiency
- Josef Weidendorfer, Tilman Küstner, Sally A. McKee:
Performance optimization by dynamic code transformation. 7 - Emmanuel Arzuaga, David R. Kaeli:
Increasing power/performance resource efficiency on virtualized enterprise servers. 8 - Karthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham:
A reconfigurable cache architecture for energy efficiency. 9 - Karl-Filip Faxén, John Ardelius:
Manycore work stealing. 10 - Alessio Franceschelli, Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Martino Ruggiero, Michele Lombardi, Alessio Bonfietti, Michela Milano, Luca Benini:
MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor. 11 - Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid high-performance low-power and ultra-low energy reliable caches. 12 - Ju-Young Jung, Sangyeun Cho:
Dynamic co-management of persistent RAM main memory and storage resources. 13 - Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Cluster-based topologies for 3D stacked architectures. 14 - Sergio Davies, Alexander D. Rast, Francesco Galluppi, Steve B. Furber:
Maintaining real-time synchrony on SpiNNaker. 15
Architectural issues for multicore and multichip processing
- Atsuya Okazaki, Yasunao Katayama, Seiji Munetoh:
Universal optical multi-drop bus for heterogeneous memory architecture. 16 - Victoria Caparrós Cabezas, Phillip Stanley-Marbell:
Quantitative analysis of parallelism and data movement properties across the Berkeley computational motifs. 17 - Riyaz Haque, David M. Peixotto, Vivek Sarkar:
CnC-Hadoop: a graphical coordination language for distributed multiscale parallelism. 18 - Francesca Palumbo, Danilo Pani, Andrea Deidda, Luigi Raffo:
Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability. 19 - Ahsan Shabbir, Sander Stuijk, Akash Kumar, Henk Corporaal, Bart Mesman:
An MPSoC design approach for multiple use-cases of throughput constrainted applications. 20 - Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang:
AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs. 21 - Masana Murase, Hideaki Komatsu, Kumiko Maeda, Shigeho Noda, Munehiro Doi, Ryutaro Himeno:
A parallel programming framework orchestrating multiple languages and architectures. 22 - Jude Angelo Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink:
Composable local memory organisation for streaming applications on embedded MPSoCs. 23 - Mouad Bahi, Christine Eisenbeis:
Rematerialization-based register allocation through reverse computing. 24
Dynamic binary translation
- Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura:
On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system. 25 - Guilherme Ottoni, Thomas Hartin, Christopher T. Weaver, Jason Brandt, Belliappa Kuttanna, Hong Wang:
Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture. 26
Performance and parallelization tools
- Ashwin M. Aji, Mayank Daga, Wu-chun Feng:
Bounding the effect of partition camping in GPU kernels. 27 - Romain Cledat, Kaushik Ravichandran, Santosh Pande:
Leveraging data-structure semantics for efficient algorithmic parallelism. 28
Applications on multicore and accelerators
- Alexander Heinecke, Dirk Pflüger:
Multi- and many-core data mining with adaptive sparse grids. 29 - Faizur Rahman, Qing Yi, Apan Qasem:
Understanding stencil code performance on multicore architectures. 30 - Sebastián Isaza, Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Georgi Gaydadjiev:
Parametrizing multicore architectures for multiple sequence alignment. 31 - Liu Peng, Aiichiro Nakano, Guangming Tan, Priya Vashishta, Dongrui Fan, Hao Zhang, Rajiv K. Kalia, Fenglong Song:
Performance analysis and optimization of molecular dynamics simulation on Godson-T many-core processor. 32
Quantum computing, wireless networks, thread scheduling
- Shruti Patil, David J. Lilja:
Performing bitwise logic operations in cache using spintronics-based magnetic tunnel junctions. 33 - Zhenbo Zhu, Parul Gupta, Qing Wang, Shivkumar Kalyanaraman, Yonghua Lin, Hubertus Franke, Smruti R. Sarangi:
Virtual base station pool: towards a wireless network cloud for radio access networks. 34 - Kishore Kumar Pusukuri, David Vengerov, Alexandra Fedorova, Vana Kalogeraki:
FACT: a framework for adaptive contention-aware thread migrations. 35
Defect-tolerant design and security
- Nawab Ali, Sriram Krishnamoorthy, Mahantesh Halappanavar, Jeff Daily:
Tolerating correlated failures for generalized Cartesian distributions via bipartite matching. 36 - Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri:
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors. 37
Memory management, virtual machines and power consumption
- Dong Li, Kirk W. Cameron, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz:
Scalable memory registration for high performance networks using helper threads. 38 - Hui Wang, Peter J. Varman:
A flexible approach to efficient resource sharing in virtualized environments. 39 - Arun Rangasamy, Y. N. Srikant:
Evaluation of dynamic voltage and frequency scaling for stream programs. 40
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