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ORCIDISSoC 2013: Tampere, Finland
- Jari Nurmi, Peeter Ellervee, Leandro Soares Indrusiak, Olli Vainio, Sarang Thombre, Jussi Raasakka:
2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013. IEEE 2013, ISBN 978-1-4799-1189-9 - Artur Mariano, Paulo Garcia, Tiago Gomes
:
SW and HW speculative Nelder-Mead execution for high performance unconstrained optimization. 1-5 - Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski:
Evaluating the scalability of test buses. 1-6 - Upasna Vishnoi, Tobias G. Noll:
A family of modular area- and energy-efficient QRD-accelerator architectures. 1-8 - Benedikt Noethen, Oliver Arnold, Gerhard P. Fettweis:
On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs. 1-7 - Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker:
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. 1-8 - Spiridon F. Beldianu, Sotirios G. Ziavras:
Efficient on-chip vector processing for multicore processors. 1-4 - Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch:
Efficient distributed memory management in a multi-core H.264 decoder on FPGA. 1-4 - Marcelo Ruaro, Everton Alceu Carara, Fernando Gehm Moraes:
Adaptive QoS techniques for NoC-based MPSoCs. 1-6 - Zheng Zhou, Karol Desnos, Maxime Pelcat, Jean-François Nezan, William Plishker, Shuvra S. Bhattacharyya:
Scheduling of parallelized synchronous dataflow actors. 1-10 - Florian Stock, Andreas Koch, Dietmar Hildenbrand:
FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler. 1-6 - Purnachand Nalluri, Luís Nero Alves, Antonio Navarro:
A novel SAD architecture for variable block size motion estimation in HEVC video coding. 1-4 - Antti Kamppi, Lauri Matilainen, Joni-Matti Määttä, Erno Salminen, Timo D. Hämäläinen:
Extending IP-XACT to embedded system HW/SW integration. 1-8 - Arttu Leppakoski, Erno Salminen, Timo D. Hämäläinen:
Framework for industrial embedded system product development and management. 1-6 - Federico Terraneo, Davide Zoni, William Fornaciari:
A cycle accurate simulation framework for asynchronous NoC design. 1-8 - Mariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid:
Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. 1-4 - Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. 1-8 - Joni-Matti Määttä, Mikko Honkonen, Tommi Korhonen, Erno Salminen, Timo D. Hämäläinen:
Dependency analysis and visualization tool for Kactus2 IP-XACT design framework. 1-6 - Essi Suikkanen, Janne Janhunen, Shahriar Shahabuddin, Markku J. Juntti:
Study of adaptive detection for MIMO-OFDM systems. 1-4 - Maximilian Odendahl, Jerónimo Castrillón, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
Split-cost communication model for improved MPSoC application mapping. 1-8 - Jamie Garside, Neil C. Audsley:
Prefetching across a shared memory tree within a Network-on-Chip architecture. 1-4 - Goran Panic, Oliver Schrape, Thomas Basmer, Frank Vater, Klaus Tittelbach-Helmrich:
TNODE: A low power sensor node processor for secure wireless networks. 1-4 - Zahra Shirmohammadi, Seyed Ghassem Miremadi:
Crosstalk avoidance coding for reliable data transmission of network on chips. 1-4 - Guilherme Montez Guindani, Fernando Gehm Moraes:
Achieving QoS in NoC-based MPSoCs through Dynamic Frequency Scaling. 1-6 - Che-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, An-Yeu Wu:
Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems. 1-4 - Lorenzo Zuolo, Gabriele Miorandi, Cristian Zambelli, Piero Olivo, Davide Bertozzi:
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems. 1-6 - Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
Comparison of analog transactions using statistics. 1-6 - Marco Balboni, Francisco Triviño, José Flich, Davide Bertozzi:
Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms. 1-6
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