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ORCIDNGCAS 2018: Valletta, Malta
- 2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, November 20-23, 2018. IEEE 2018, ISBN 978-1-5386-7681-3
- Hua Fan, Chen Wang, Hailiang Xiong, Quanyuan Feng, Dagang Li, Kelin Zhang, Xiaopeng Diao, Lishuang Lin, Hadi Heidari
:
A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). 1-4 - Suyash Kumar, Gunit Dhingra, Pragati Kumar:
Variable Transconductance Voltage Differencing Current Conveyor and its Application in Filter Design. 5-8 - J. Sotiere, Mehdi Terosiet, Edwin De Roux, Alejandro Von Chong, Florian Kölbl, Aymeric Histace, Olivier Romain:
Versatile SAR-ADC for Biomedical Applications. 9-12 - Raul Blecic, Josip Bacmaga, Adrijan Baric, Fabio Pareschi, Riccardo Rovatti, Gianluca Setti:
Impact of the Spread-Spectrum Technique on the Higher-Order Harmonics and Radiated Emissions of a Synchronous Buck Converter. 13-16 - Andrea De Marcellis, Elia Palange, Simona Leone, Guido Di Patrizio Stanchieri, Marco Faccio:
Photodiode Bridge-Based Differential Readout Circuit for High-Sensitivity Measurements of Energy Variations of Laser Pulses for Optoelectronic Sensing Systems. 17-20 - Cristian Zambelli, Marco Castellari, Piero Olivo, Davide Bertozzi:
Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs. 21-24 - Jan Nevoral, Richard Ruzicka:
Efficient Implementation of Bi-Functional RTL Components - Case Study. 25-28 - Riccardo Matera, Valentino Meacci, Stefano Rossi, Dario Russo, Stefano Ricci, Didier Lootens:
Smart Ultrasound Sensor for Non-Destructive Tests. 29-32 - Dario Russo, Valentino Meacci, Stefano Ricci:
Profile Generator for Ultrasound Doppler Systems. 33-36 - Kelby Haulmark, Wassim Khalil, William Bouillon, Jia Di:
Comprehensive Comparison of NULL Convention Logic Threshold Gate Implementations. 37-40 - Valentino Meacci, Riccardo Matera, Dario Russo, Stefano Ricci:
Torque-Oriented Stepper Motor Control in FPGA. 41-44 - Clive Seguna, Edward Gatt, Jordan Lee Gauci, Giacinto De Cataldo, Ivan Grech, Owen Casha:
A New FPGA-Based Controller Card for the Optimisation of the Front-End Readout Electronics of Charged-Particle Veto Detector at ALICE. 45-48 - Amr Abbas, Hassan Mostafa, Ahmed Nader Mohieldin:
Low Area and Low Power Implementation for CAESAR Authenticated Ciphers. 49-52 - Miguel R. Weirich, Guilherme Paim, Eduardo A. C. da Costa, Sergio Bampi:
A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series. 53-56 - Ahmed Mahmoud, Loay Ehab, Mohamed Reda, Mostafa Abdelaleem, Hossam Abd El Munim, Maged Ghoneima, M. Saeed Darweesh, Hassan Mostafa:
Real-Time Lane Detection-Based Line Segment Detection. 57-61 - William Agius, Kris Scicluna, Joseph Zammit, Clive Seguna, Jeremy Scerri:
Design of an STM32F4 Microcontroller Development Board for Switching Power Converters. 62-65 - Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. 66-69 - Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro:
Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. 70-73 - Josip Bacmaga, Raul Blecic, Roger Voaden, Adrijan Baric:
Characterization of Digital IC for Sub-Nanosecond Dead-Time Adjustment Used in Synchronous DC-DC Converters. 74-77 - Mauro Mangia, Letizia Magenta, Alex Marchioni, Fabio Pareschi, Riccardo Rovatti, Gianluca Setti:
Projected-Gradient-Descent in Rakeness-Based Compressed Sensing with Disturbance Rejection. 78-81 - Johannes Wagner, Patrick Vogelmann, Maurits Ortmanns:
On the Optimization of DT Incremental Sigma-Delta Modulators in Combination with CoI Reconstruction Filters. 82-85 - Ryota Tsuchihashi, Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura:
Task Allocation and Scheduling Optimization in the Heterogeneous Core System. 86-89 - Johannes Wagner, Felix Vogel, Florian Kuhm, Maurits Ortmanns:
Automated Synthesis of Subsampling CT Bandpass ΣΔ Modulators with Non-Idealities. 90-93 - Tomohiro Takahashi, Yasuhiro Takashima:
Fast Approximate Algorithm for the Single Source Shortest Path with Lazy Update. 94-97 - Celal Erbay, Salih Ergun:
Random Number Generator Based on Fuel Cells. 98-101 - Zdenek Kolka, Viera Biolková, Dalibor Biolek, Zdenek Biolek:
Hardware Implementation of Bio-Inspired Models. 102-105 - Kaya Demir, Salih Ergun:
Analytical Modeling of Continuous-Time Chaos Based Random Number Generators. 106-109 - Moustafa Saleh, Ali Ibrahim, Flavio Ansovini, Yasser Mohanna, Maurizio Valle:
Wearable System for Sensory Substitution for Prosthetics. 110-113 - Reem Abd El-Sttar, Endy Onsy, George S. Maximous, Ahmed Zaky, Tamer A. Ali, Ashraf Seleym, Hassan Mostafa:
Diagonal Mode: A New Mode for Triboelectric Anogenerators Energy Harvesters. 114-117 - Raul Blecic, Josip Bacmaga, Adrijan Baric:
Characterization and Equivalent Circuit Model of 500-MHz Two-Port Electromagnetic Resonant Couplers for Isolated Gate Drivers. 118-121 - Kris Scicluna, Cyril Spiteri Staines, Reiko Raute:
Sensorless Position Trackingi in Steer-by-Wire Using the SONIC Method. 122-125 - Clive Seguna, Adrian von Brockdorff, Jeremy Scerri, Kris Scicluna:
Development of a New Low-Cost EMG Monitoring System for the Classification of Finger Movement. 126-129 - Aly Sultan, Ali H. Hassan, Hassan Mostafa:
A Compact Low-Power Mitchell-Based Error Tolerant Multiplier. 130-133 - Maicon Robe Ferreira, Sérgio Jose Melo de Almeida, Eduardo Antonio Cesar da Costa:
Power System Frequency Estimation U Sing the Kernel Least Mean Square Algorithm and the Clarke Transform. 134-137 - Chao Geng, Shigetoshi Nakatake:
Hierarchical Floorplanning Based on Analog Structure Tree. 138-141 - Xuncheng Zou, Shigetoshi Nakatake:
Analog Retargeting Constraint Extraction Based on Fundamental Circuits and Layout Regularity. 142-145 - Kashif Nawaz, Itamar Levi, François-Xavier Standaert, Denis Flandre:
A Transient Noise Analysis of Secured Dual-Rail Based Logic Style. 146-149 - Hua Fan, Xinjie Wu, Tao Zhang, Quanyuan Feng, Lang Feng, Dagang Li, Kelin Zhang, Daqian Hu, Yuanjun Cen, Hadi Heidari:
High-Resolution ADCs for Biomedical Imaging Systems. 150-153 - Julia Farrugia, Carl James Debono:
Texture Super-Resolution in Multiview RGB-D Transmission. 154-157 - Sherif Hosny, Eslam Elnader, Mostafa Gamal, Abdelrhman Hussien, Ahmed H. Khalil, Hassan Mostafa:
A Software Defined Radio Transceiver Based on Dynamic Partial Reconfiguration. 158-161 - D. Prevcdelli, Giacomo Pini, Danilo Manstretta, Rinaldo Castello:
A Mixer-1st Auxiliary Receiver for Full-Duplex Self-Interference Cancellation. 162-165 - Yury Antonov, Markus Törmänen, Jussi Ryynänen, Aarno Pärssinen, Kari Stadius:
A 20-60GHz Digitally Controlled Composite Oscillator for 5G. 166-169 - Ming-Hsuan Lai, Tzi-Dar Chiueh:
Implementation of a C-V2X Receiver on an Over-the-Air Software-Defined-Radio Platform with OpenCL. 170-173 - Giovanni Piccinni, Gianfranco Avitabile, Giuseppe Coviello, Claudio Talarico:
Modeling of a Re-Configurable Indoor Positioning System Based on Software Defined Radio Architecture. 174-177 - Khaled Salah, Hassan Mostafa:
Constructing Effective UVM Testbench for DRAM Memory Controllers. 178-181 - Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. 182-185 - Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters. 186-189 - Alberto Paltrinieri, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina:
Approximate-Computing Architectures for Motion Estimation in HEVC. 190-193 - Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas:
Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module. 194-197
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