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ORCID6th NorCAS 2020: Oslo, Norway
- Jari Nurmi, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard:
IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, Norway, October 27-28, 2020. IEEE 2020, ISBN 978-1-7281-9226-0 - Marko Neitola:
Digital Timing Error Calibration of Time-Interleaved ADC with Low Sample Rate. 1-7 - Aidan O'Mahony, Gil Zeidan, Bernard Hanzon, Emanuel M. Popovici:
A Parallel and Pipelined Implementation of a Pascal-Simplex Based Two Asset Option Pricer on FPGA using OpenCL. 1-6 - Max Koenen
, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs. 1-7 - Timmy Sundström, Javad Bagheri Asli, Christer Svensson, Atila Alvandpour:
A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS. 1-4 - Madhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder:
A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range. 1-5 - Seyed Ruhallah Qasemi, Maryam Rafati, Atila Alvandpour:
A Low Power Front-end for Biomedical Fluorescence Sensing Applications. 1-6 - Ted Johansson, Srivatsa Samji:
On the Design of a CMOS-integrated Load Modulated Balanced Amplifier. 1-4 - Shahriar Shahabuddin, Muhammad Hasibul Islam, Mohammad Shahanewaz Shahabuddin, Mahmoud A. M. Albreem, Markku J. Juntti:
Matrix Decomposition for Massive MIMO Detection. 1-6 - Siyu Tan, Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström, Sven Mattisson, Pietro Andreani:
A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs. 1-6 - Negar Shabanzadeh, Mahmoud Shehab, Rehman Akbar, Aarno Pärssinen, Timo Rahkonen:
Origins of Intermodulation Distortion in A Pseudo-differential CMOS Beamforming Receiver. 1-6 - Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet:
Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. 1-6 - Giovanni Mezzina, Daniela De Venuto:
Digital Architecture for MUAPs Propagation Speed Estimator triggered by Foot Plant Switch. 1-7 - Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek:
A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS. 1-4 - Simon Buhr, Martin Kreißig, Christian D. Matthus, Florian Protze, Frank Ellinger:
Low Power Class-AB Line Driver with Adaptive Digital Impedance Control for Fast Ethernet. 1-7 - Vincenzo Bonaiuto, Fausto Sargeni:
Design of a Current Mode Multiplexed Circuit for Integrate & Fire Neuromorphic Systems. 1-6 - Piyush Kumar, Dario Stajic, Enno Böhme, Erkan Nevzat Isa, Linus Maurer:
A 500 mV, 4.5 mW, 16 GHz VCO with 33.3% FTR, designed for 5G applications. 1-4 - Dionisio Carvalho, Alexandre J. Aragão, André Ferrari, Bruno Sanches, Wilhelmus A. M. Van Noije:
Software-Defined Radio Assessment for Microwave Imaging Breast Cancer Detection. 1-6 - Cornelia Wulf, Michael Willig, Diana Göhringer:
Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAs. 1-7 - Lizheng Liu, Deyu Wang, Yuning Wang, Anders Lansner, Ahmed Hemani, Yu Yang, Xiaoming Hu, Zhuo Zou, Lirong Zheng:
A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network. 1-6 - Yasir Shafiullah, Rehman Akbar, Mikko Hietanen, Aarno Pärssinen:
A Voltage Controlled Oscillator with Inductive Divider Design and Analysis at Frequencies Above 100 GHz. 1-5 - Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet:
Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. 1-6 - Luis Henrique Rodovalho:
Schmitt Trigger Based Single-Ended Voltage Amplifier with Positive Feedback Control for Ultra-Low-Voltage Supplies. 1-6 - Shashank Awasthi, Saurav Sharma, Sanjeev Kumar Metya, Alak Majumder:
Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder Interferometers. 1-7 - Jessé Barreto de Barros, Nidhi Anantharajaiah, Mauricio Ayala-Rincón, Carlos Humberto Llanos Quintero, Jürgen Becker:
A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCs. 1-7 - Erwin H. T. Shad, Tania Moeinfard, Marta Molinas, Trond Ytterdal:
A Power Efficient, High Gain and High Input Impedance Capacitively-coupled Neural Amplifier. 1-5 - Akshay Srivatsa, Sebastian Nagel, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
HyVE: A Hybrid Voting-based Eviction Policy for Caches. 1-7 - Server Kasap, Eduardo Weber Wächter, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier:
Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors. 1-7 - Manu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele:
Model-Based Design Space Exploration for Approximate Image Processing on FPGA. 1-7 - Ameer M. S. Abdelhadi:
Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol. 1-7
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last updated on 2024-11-15 19:19 CET by the dblp team
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