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Computer Architecture Letters, Volume 3

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Volume 3, January - December 2004

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Daniel Citron:
Exploiting Low Entropy to Reduce Wire Delay.
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Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta:
Globally Adaptive Load-Balanced Routing on Tori.
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María Engracia Gómez, José Duato, José Flich, Pedro López, Antonio Robles, Nils Agne Nordbotten, Olav Lysne, Tor Skeie:
An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori.
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Jeffrey M. Stine, Nicholas P. Carter, José Flich:
Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction.
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Behnam Robatmili, Nasser Yazdani, Somayeh Sardashti, Mehrdad Nourani:
Thread-Sensitive Instruction Issue for SMT Processors.
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Yue Luo, Lizy K. John:
Efficiently Evaluating Speedup Using Sampled Processor Simulation.
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Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas:
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction.
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Arjun Singh, William J. Dally:
Buffer and Delay Bounds in High Radix Interconnection Networks.
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Allison L. Holloway, Gurindar S. Sohi:
Characterization of Problem Stores.

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