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ORCIDShuichi Tahara
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2000 – 2009
- 2007
[j5]Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara:
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. IEICE Trans. Electron. 90-C(2): 531-535 (2007)- [j4]Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai:
MRAM Applications Using Unlimited Write Endurance. IEICE Trans. Electron. 90-C(10): 1936-1940 (2007) - [j3]Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo
, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara:
MRAM Cell Technology for Over 500-MHz SoC. IEEE J. Solid State Circuits 42(4): 830-838 (2007) - [j2]Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara:
A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits 42(11): 2378-2385 (2007) - [c3]Eugenio Cantatore, Shuichi Tahara:
TD: Emerging Devices Devices and Circuits. ISSCC 2007: 60-61 - 2006
- [c2]Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda:
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ISSCC 2006: 477-486 - 2003
- [c1]Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda:
Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro. CICC 2003: 399-402
1980 – 1989
- 1989
- [j1]Shuichi Nagasawa, Yoshifusa Wada, Mutsuo Hidaka, Hisanao Tsuge, Iichiro Ishida, Shuichi Tahara:
570-ps 13-mW Josephson 1-kbit NDRO RAM. IEEE J. Solid State Circuits 24(5): 1363-1371 (1989)
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