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2020 – today
- 2024
[j14]Jaehoon Jeong
, Yunjeong Shin, Hyundong Lee, JongHyun Ko, Jongbeom Kim, Taigon Song:
Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node. IEEE Access 12: 97557-97571 (2024)- [c26]Seungmin Woo, Hyunsoo Lee, Yunjeong Shin, MinSeok Han, Yunjeong Go, Jongbeom Kim, Hyundong Lee, Hyunwoo Kim, Taigon Song:
Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction. DATE 2024: 1-6 - [c25]Yunjeong Shin, Daehyeok Park, Dohun Koh, Dongryul Heo, Jieun Park, Hyundong Lee, Jongbeom Kim, Hyunsoo Lee, Taigon Song:
FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond. ISCAS 2024: 1-5 - 2023
- [j13]JongHyun Ko, Jongbeom Kim, TaeGam Jeong, Jaehoon Jeong, Taigon Song:
Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3612-3624 (2023) - [j12]Jongbeom Kim, Hyundong Lee, JongHyun Ko, Bongjun Kim, Taigon Song:
T3L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4826-4839 (2023) - [j11]Taehak Kim, Jaehoon Jeong, Seungmin Woo, Jeonggyu Yang, Hyunwoo Kim, Ahyeon Nam, Changdong Lee, Jinmin Seo, Minji Kim, Siwon Ryu, Yoonju Oh, Taigon Song:
NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 163-176 (2023) - [j10]Eun-Bin Park, Taigon Song:
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 177-187 (2023) - [c24]Hyunsoo Lee, Hyundong Lee, Minseung Shin, Gyuri Shin, Sumin Jeon, Taigon Song:
High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. ISOCC 2023: 101-102 - [c23]MinSeung Shin, Jongbeom Kim, Yunjeong Shin, Taigon Song:
A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond. ISOCC 2023: 119-120 - [c22]MinSeok Han, Jiwan Kim, Donggeon Kim, Hyunuk Jeong, Gilho Jung, Myeongwon Oh, Hyundong Lee, Yunjeong Go, HyunWoo Kim, Jongbeom Kim, Taigon Song:
HFGCN: High-speed and Fully-optimized GCN Accelerator. ISQED 2023: 1-7 - [c21]Hyunwoo Kim, Hyundong Lee, Jongbeom Kim, Yunjeong Go, Seungwon Baek, Jaehong Song, Junhyeon Kim, Minyoung Jung, Hyodong Kim, Seongju Kim, Taigon Song:
Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory. ISQED 2023: 1-6 - 2022
- [j9]Jeonggyu Yang, Hyundong Lee, Jaehoon Jeong, Taehak Kim, Sin-Hyung Lee, Taigon Song:
Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 707-720 (2022) - [c20]Jaehoon Jeong, JongHyun Ko, Taigon Song:
A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node. ISLPED 2022: 16:1-16:6 - [c19]Jongbeom Kim, Yeji Kim, Hyundong Lee, Jihyeong Yun, Hyeseung Jang, Huijeen Jin, Juhee Park, Bongjun Kim, Taigon Song:
A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes. ISMVL 2022: 15-20 - [c18]Hyundong Lee, Hyeseung Jang, Jihyeong Yun, Huijeen Jin, Jongbeom Kim, Yeji Kim, Taigon Song:
Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs. ISMVL 2022: 21-26 - [c17]Hyunwoo Kim, Seungwon Baek, Jaehong Song, Taigon Song:
A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory. ISOCC 2022: 127-128 - 2021
- [c16]Taehak Kim, Jaehoon Jeong, Seungmin Woo, Jeonggyu Yang, Hyunwoo Kim, Ahyeon Nam, Changdong Lee, Jinmin Seo, Minji Kim, Siwon Ryu, Yoonju Oh, Taigon Song:
NS3K: A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes. ISCAS 2021: 1-5 - [c15]Jeonggyu Yang, Hyundong Lee, Jaehoon Jeong, Taehak Kim, Sin-Hyung Lee, Taigon Song:
A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs. ISMVL 2021: 183-188 - [c14]JongHyun Ko, KwanWoo Park, Suhyeong Yong, TaeGam Jeong, Taehak Kim, Taigon Song:
An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS. ISMVL 2021: 189-194 - [c13]Eun-Bin Park, Taigon Song:
An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs). ISOCC 2021: 395-396 - 2020
- [j8]Taigon Song:
Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm. IEEE Access 8: 149984-149998 (2020) - [c12]Jeonggyu Yang, Taigon Song:
A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption. ISOCC 2020: 310-311
2010 – 2019
- 2017
- [j7]Moongon Jung, Taigon Song, Yarui Peng, Sung Kyu Lim:
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2109-2117 (2017) - [c11]Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, Sung Kyu Lim:
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. ISLPED 2017: 1-6 - 2016
- [j6]Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim:
More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2056-2067 (2016) - [j5]Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim:
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1636-1648 (2016) - 2015
- [j4]Taigon Song, Sung Kyu Lim:
Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs. J. Inform. and Commun. Convergence Engineering 13(3) (2015) - [j3]Taigon Song, Sung Kyu Lim:
Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits. J. Inform. and Commun. Convergence Engineering 13(3) (2015) - [j2]Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015) - [c10]Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim:
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. ICCAD 2015: 649-655 - [c9]Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim:
Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection. ICCAD 2015: 752-757 - 2014
- [j1]Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim:
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1900-1913 (2014) - [c8]Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, Sung Kyu Lim:
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. DAC 2014: 4:1-4:6 - 2013
- [c7]Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim:
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. CICC 2013: 1-4 - [c6]Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim:
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. DAC 2013: 180:1-180:7 - [c5]Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim:
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. ICCAD 2013: 281-288 - 2012
- [c4]Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 - 2011
- [c3]Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim:
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. DAC 2011: 783-788 - [c2]Chang Liu, Taigon Song, Sung Kyu Lim:
Signal integrity analysis and optimization for 3D ICs. ISQED 2011: 42-49 - [c1]Taigon Song, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon:
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. ISQED 2011: 122-128
Coauthor Index
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