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2010 – 2019
- 2011
[c12]Toshiya Takami
, Akira Nishida:
Parareal Acceleration of Matrix Multiplication. PARCO 2011: 437-444- 2010
- [c11]Akira Nishida:
Experience in Developing an Open Source Scalable Software Infrastructure in Japan. ICCSA (2) 2010: 448-462 - [p1]Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehiko Hasegawa, Akira Nishida:
Toward Automatic Performance Tuning for Numerical Simulations in the SILC Matrix Computation Framework. Software Automatic Tuning, From Concepts to State-of-the-Art Results 2010: 175-192
2000 – 2009
- 2007
- [c10]Akira Nukada, Daisuke Takahashi, Reiji Suda, Akira Nishida:
High Performance FFT on SGI Altix 3700. HPCC 2007: 396-407 - [c9]Akira Nukada, Yuichiro Hourai, Akira Nishida, Yutaka Akiyama:
High Performance 3D Convolution for Protein Docking on IBM Blue Gene. ISPA 2007: 958-969 - [c8]Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehiko Hasegawa, Akira Nishida:
Cloth Simulation in the SILC Matrix Computation Framework: A Case Study. PPAM 2007: 1086-1095 - 2006
- [c7]Akira Nishida:
Building Cost Effective High Performance Computing Environment via PCI Express. ICPP Workshops 2006: 519-526 - [c6]Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehiko Hasegawa, Akira Nishida:
Distributed SILC: An Easy-to-Use Interface for MPI-Based Parallel Matrix Computation Libraries. PARA 2006: 860-870 - [c5]Akira Nishida, Hisashi Kotakemori, Tamito Kajiyama, Akira Nukada:
Poster reception - Scalable software infrastructure project. SC 2006: 140 - 2005
- [c4]Yuichiro Hourai, Akira Nishida, Yoshio Oyanagi:
Network-aware Data mMapping on Parallel Molecular Dynamicas. ICPADS (1) 2005: 126-132 - [c3]Hisashi Kotakemori, Hidehiko Hasegawa, Tamito Kajiyama, Akira Nukada, Reiji Suda, Akira Nishida:
Performance Evaluation of Parallel Sparse Matrix-Vector Products on SGI Altix3700. IWOMP 2005: 153-163 - [c2]Tamito Kajiyama, Akira Nukada, Hidehiko Hasegawa, Reiji Suda, Akira Nishida:
SILC: A Flexible and Environment-Independent Interface for Matrix Computation Libraries. PPAM 2005: 928-935 - 2003
- [c1]Akira Nishida, Yoshio Oyanagi:
Performance Evaluation of Low Level Multithreaded BLAS Kernels on Intel Processor Based cc-NUMA Systems. ISHPC 2003: 500-510
1990 – 1999
- 1999
- [j2]Toshiro Takahashi, Takashi Muto, Yuji Shirai, Fumihiko Shirotori, Yoshifumi Takada, Akira Yamagiwa, Akira Nishida, Atsuo Hotta, Tadashi Kiyuna:
110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock. IEEE J. Solid State Circuits 34(11): 1526-1533 (1999) - [j1]Reiji Suda, Akira Nishida, Yoshio Oyanagi:
A high performance parallelization scheme for the Hessenberg double shift QR algorithm. Parallel Comput. 25(6): 729-744 (1999)
Coauthor Index
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