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ORCIDCaaliph Andriamisaina
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2010 – 2019
- 2019
[j5]Laurent Millet
, Stéphane Chevobbe, Caaliph Andriamisaina, Lamine Benaissa, Edouard Deschaseaux, Edith Beigné, Karim Ben Chehida, Maria Lepecq, Mehdi Darouich, Fabrice Guellec, Thomas Dombek, Marc Duranton:
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing. IEEE J. Solid State Circuits 54(4): 1096-1105 (2019)- [c8]Arief Wicaksana, Amir Charif, Caaliph Andriamisaina, Nicolas Ventroux:
Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design. DASIP 2019: 35-40 - 2018
- [c7]Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, Lamine Benaissa, Edouard Deschaseaux, Marc Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq:
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing. VLSI Circuits 2018: 245-246 - 2014
- [j4]Yves Lhuillier, Maroun Ojail, Alexandre Guerre, Jean-Marc Philippe, Karim Ben Chehida, Farhat Thabet, Caaliph Andriamisaina, Chafic Jaber, Raphaël David:
HARS: A hardware-assisted runtime software for embedded many-core architectures. ACM Trans. Embed. Comput. Syst. 13(3s): 102:1-102:25 (2014) - 2013
- [c6]Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, Raphaël David:
An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture. DATE 2013: 531-534 - 2010
- [j3]Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet:
High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1736-1749 (2010)
2000 – 2009
- 2008
- [j2]Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina:
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. Tech. Sci. Informatiques 27(9-10): 1129-1154 (2008) - 2007
- [c5]Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy:
Synthesis of Multimode digital signal processing systems. AHS 2007: 318-325 - [c4]Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD 2007: 604-611 - 2006
- [j1]Catherine Dezan, Erwan Fabiani, Christophe Gouyen, Loïc Lagadec, Bernard Pottier, Caaliph Andriamisaina, Alix Poungou:
Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques. Tech. Sci. Informatiques 25(7): 893-920 (2006) - [c3]Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau:
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. SiPS 2006: 280-285 - [c2]Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau:
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. SoCC 2006: 175-178 - 2005
- [c1]Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier:
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. ERSA 2005: 263-266
Coauthor Index
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