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2020 – today
- 2024
[j124]Minkyo Shim
, Seungha Roh, Yunhee Lee, Jung-Woo Sull, Deog-Kyoon Jeong, Kwanseo Park:
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3550-3560 (2024)- [j123]Seungha Roh, Minkyo Shim, Yoojin Jung, Deog-Kyoon Jeong, Kwanseo Park:
A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR. IEEE Trans. Circuits Syst. I Regul. Pap. 71(12): 5861-5872 (2024) - 2023
- [j122]Minkyo Shim, Woonghee Lee, Yunhee Lee, Kwanseo Park, Deog-Kyoon Jeong:
A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link. IEEE Access 11: 46513-46521 (2023) - [j121]Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong:
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. IEEE J. Solid State Circuits 58(5): 1414-1424 (2023) - [j120]Jonghyun Oh, Young-Ha Hwang, Jun-Eun Park, Mingoo Seok, Deog-Kyoon Jeong:
An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector. IEEE J. Solid State Circuits 58(6): 1769-1781 (2023) - [j119]Minkyo Shim, Kwang-Hoon Lee, Seungha Roh, Kwanseo Park, Deog-Kyoon Jeong:
A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 381-385 (2023) - [j118]Yunhee Lee, Minkyo Shim, Seungha Roh, Woonghee Lee, Deog-Kyoon Jeong:
An 80-Gb/s PAM-4 Simultaneous Bidirectional Transceiver With Hybrid Adaptation Scheme. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2884-2888 (2023) - [j117]Sanghee Lee, Byungjun Kang, Woogeun Rhee, Deog-Kyoon Jeong:
A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 3998-4002 (2023) - [j116]Kwang-Hoon Lee, Jung-Hun Park, Yongjae Lee, Yeonggeun Song, Seungha Roh, Minkyo Shim, Yoonho Song, Woosong Jung, Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong:
A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4003-4007 (2023) - [j115]Young-Ha Hwang, Jun Wang, Deog-Kyoon Jeong, Jun-Eun Park:
An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1403-1412 (2023) - [c94]Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong:
A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. A-SSCC 2023: 1-3 - [c93]Woosong Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong:
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces. CICC 2023: 1-2 - [c92]Woosong Jung, Minkyo Shim, Seungha Roh, Deog-Kyoon Jeong:
A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector. ISCAS 2023: 1-5 - [c91]Kahyun Kim, Daeho Yun, Kyungmin Baek, Woo-Seok Choi, Deog-Kyoon Jeong:
A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. ISCAS 2023: 1-5 - [c90]Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong:
A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. ISSCC 2023: 410-411 - [c89]Jung-Woo Sull, Minkyo Shim, Jung-Hun Park, Sanghee Lee, Deog-Kyoon Jeong:
An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS. MWSCAS 2023: 1005-1009 - 2022
- [j114]Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong:
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. IEEE J. Solid State Circuits 57(2): 573-585 (2022) - [j113]Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong:
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. IEEE J. Solid State Circuits 57(6): 1712-1722 (2022) - [j112]Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park:
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. IEEE J. Solid State Circuits 57(7): 2236-2249 (2022) - [j111]Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong:
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. IEEE J. Solid State Circuits 57(10): 3014-3024 (2022) - [j110]Yeonggeun Song, Han-Gon Ko, Changhyun Kim, Deog-Kyoon Jeong:
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 759-763 (2022) - [j109]Soyeong Shin, Yongjae Lee, Jiheon Park, Jihyo Kang, Kyunghoon Kim, Dae-Han Kwon, Sangkwon Lee, Jieun Jang, Joo-Hwan Cho, Deog-Kyoon Jeong:
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 814-818 (2022) - [j108]Jung-Woo Sull, Soyeong Shin, Jonghyun Oh, Kwang-Hoon Lee, Jihee Kim, Jung-Hun Park, Deog-Kyoon Jeong:
An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 874-878 (2022) - [j107]Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong:
Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2056-2060 (2022) - [j106]Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong:
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2677-2681 (2022) - [j105]Seungha Roh, Kwangho Lee, Minkyo Shim, Moon-Chul Choi, Deog-Kyoon Jeong:
A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3704-3708 (2022) - [j104]Daeho Yun, Eonhui Lee, Woosong Jung, Kahyun Kim, Kyung-Min Beak, Jihee Kim, Hyun Bae Lee, Byeongseon Ko, Woo-Seok Choi, Deog-Kyoon Jeong:
A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3749-3753 (2022) - [j103]Young-Ha Hwang, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong:
A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1381-1390 (2022) - [c88]Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong:
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC 2022: 249-252 - [c87]Kyungmin Baek, Kahyun Kim, Deog-Kyoon Jeong:
A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE. ISOCC 2022: 139-140 - [c86]Yoonho Song, Eunseo Kim, Deog-Kyoon Jeong:
Design of Energy Harvesting System with Piezoelectric Device for Onetime-High-Energy Applications. ISOCC 2022: 149-150 - [c85]Hyojun Kim, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh, Deog-Kyoon Jeong:
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration. ISSCC 2022: 1-3 - [c84]Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong:
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. VLSI Technology and Circuits 2022: 30-31 - [c83]Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong:
A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. VLSI Technology and Circuits 2022: 150-151 - 2021
- [j102]Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong:
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access 9: 156789-156798 (2021) - [j101]Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong:
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits 56(5): 1597-1607 (2021) - [j100]Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong:
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021) - [j99]Chang-Soo Yoon, Han-Gon Ko, Byung-Jun Kang, Jung-Woo Sull, Deog-Kyoon Jeong:
0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 136-140 (2021) - [j98]Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog-Kyoon Jeong:
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 622-626 (2021) - [c82]Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon Jeong:
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS. A-SSCC 2021: 1-3 - [c81]Haram Ju, Kwangho Lee, Woosong Jung, Deog-Kyoon Jeong:
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS. A-SSCC 2021: 1-3 - [c80]Kwangho Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong:
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS. A-SSCC 2021: 1-3 - [c79]Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Han-Gon Ko, Woo-Seok Choi, Deog-Kyoon Jeong:
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. ESSCIRC 2021: 475-478 - [c78]Seungha Roh, Moon-Chul Choi, Deog-Kyoon Jeong:
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS. ISOCC 2021: 47-48 - [c77]Minkyo Shim, Woonghee Lee, Yunhee Lee, Deog-Kyoon Jeong:
A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling. ISOCC 2021: 49-50 - [c76]Hong-Seok Choi, Seungha Roh, Sanghee Lee, Jung-Hoon Park, Kwanghoon Lee, Young-Ha Hwang, Deog-Kyoon Jeong:
A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS. ISOCC 2021: 127-128 - [c75]Yunhee Lee, Woonghee Lee, Minkyo Shim, Deog-Kyoon Jeong:
A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver. ISOCC 2021: 379-380 - [c74]Daeho Yun, Deog-Kyoon Jeong:
Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver. ISOCC 2021: 381-382 - 2020
- [j97]Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong:
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference. IEEE J. Solid State Circuits 55(8): 2186-2195 (2020) - [j96]Jungmin Yoon, Hyungrok Do, Daehyun Koh, Seunghan Oak, Junphyo Lee, Deog-Kyoon Jeong:
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage. IEEE J. Solid State Circuits 55(8): 2219-2227 (2020) - [j95]Hyungrok Do, Jeongho Hwang, Hong-Seok Choi, Deog-Kyoon Jeong:
A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1569-1573 (2020) - [j94]Sangyoon Lee, Han-Gon Ko, Joo-Hyung Chae, Soyeong Shin, Jaekwang Yun, Deog-Kyoon Jeong, Suhwan Kim:
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1735-1739 (2020) - [j93]Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong:
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1814-1818 (2020) - [j92]Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong:
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1834-1838 (2020) - [j91]Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong:
A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2174-2178 (2020) - [j90]Chan-Ho Kye, Han-Gon Ko, Jinhyung Lee, Deog-Kyoon Jeong:
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1099-1106 (2020) - [j89]Hye-Yoon Joo, Jinhyung Lee, Haram Ju, Han-Gon Ko, Jungmin Yoon, Byungjun Kang, Deog-Kyoon Jeong:
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2708-2720 (2020) - [c73]Tae Jun Ham, Sungjun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song, Jung-Hun Park, Sanghee Lee, Kyoung Park, Jae W. Lee, Deog-Kyoon Jeong:
A3: Accelerating Attention Mechanisms in Neural Networks with Approximation. HPCA 2020: 328-341 - [c72]Woosong Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, Deog-Kyoon Jeong:
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface. ISOCC 2020: 41-42 - [c71]Daehyun Koh, Dainel Jeong, Jeongho Hwang, Deog-Kyoon Jeong:
Optical Receiver Front-end for Active Optical Cable in 180 nm CMOS. ISOCC 2020: 43-44 - [c70]Hyojun Kim, Jun-Eun Park, Deog-Kyoon Jeong:
An Area-Efficient Temperature Compensated Sub-Threshold CMOS Voltage Reference. ISOCC 2020: 153-154 - [c69]Jung-Woo Sull, Hyungrok Do, Deog-Kyoon Jeong:
A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS. ISOCC 2020: 266-267 - [c68]Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong:
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. ISSCC 2020: 124-126 - [c67]Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong:
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. ISSCC 2020: 128-130 - [c66]Minho Choi, Deog-Kyoon Jeong:
18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor. ISSCC 2020: 296-298 - [c65]Soyeong Shin, Han-Gon Ko, Sungchun Jang, Dongkyun Kim, Deog-Kyoon Jeong:
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. ISSCC 2020: 340-342 - [c64]Jonghyun Oh, Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong:
25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density. ISSCC 2020: 382-384 - [c63]Jun-Eun Park, Jeongho Hwang, Jonghyun Oh, Deog-Kyoon Jeong:
32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement. ISSCC 2020: 492-494 - [c62]Moon-Chul Choi, Han-Gon Ko, Jonghyun Oh, Hye-Yoon Joo, Kwangho Lee, Deog-Kyoon Jeong:
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. VLSI Circuits 2020: 1-2 - [i1]Tae Jun Ham, Sungjun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song, Jung-Hun Park, Sanghee Lee, Kyoung Park, Jae W. Lee, Deog-Kyoon Jeong:
A3: Accelerating Attention Mechanisms in Neural Networks with Approximation. CoRR abs/2002.10941 (2020)
2010 – 2019
- 2019
- [j88]Han-Gon Ko, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
Reference Spur Reduction Techniques for a Phase-Locked Loop. IEEE Access 7: 38035-38043 (2019) - [j87]Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong:
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors. IEEE Access 7: 63686-63697 (2019) - [j86]Jun-Eun Park, Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Deog-Kyoon Jeong:
A Noise-Immunity-Enhanced Analog Front-End for $36\times64$ Touch-Screen Controllers With 20- $\text{V}_{\text{PP}}$ Noise Tolerance at 100 kHz. IEEE J. Solid State Circuits 54(5): 1497-1510 (2019) - [j85]Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong:
A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch Screen. IEEE J. Solid State Circuits 54(6): 1694-1704 (2019) - [j84]Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54(10): 2812-2822 (2019) - [j83]Gyu-Seob Jeong, Byungjun Kang, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong:
A Modulo-FIR Equalizer for Wireline Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4278-4286 (2019) - [j82]Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim:
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1927-1931 (2019) - [j81]Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong:
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1932-1936 (2019) - [c61]Hye-Yoon Joo, Deog-Kyoon Jeong:
A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation. A-SSCC 2019: 243-244 - [c60]Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong:
A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. ICEIC 2019: 1-4 - [c59]Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong:
A $4.7\mu \mathrm{A}$ Quiescent Current Synthesizable Digital Low Dropout Regulator in 28-nm CMOS. ICEIC 2019: 1-2 - [c58]Young-Ha Hwang, Jonghyun Oh, Jiheon Park, Yoonho Song, Jung-Hun Park, Jun-Eun Park, Deog-Kyoon Jeong:
An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC. ESSCIRC 2019: 313-316 - [c57]Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong:
A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode. ISLPED 2019: 1-6 - [c56]Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, Deog-Kyoon Jeong:
A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time. ISSCC 2019: 432-434 - [c55]Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong:
56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. OFC 2019: 1-3 - [c54]Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong:
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. VLSI Circuits 2019: 94- - [c53]Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong:
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits 2019: 194- - [c52]Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong:
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level. VLSI Circuits 2019: 198- - [c51]Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong:
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. VLSI Circuits 2019: 268- - 2018
- [j80]Kwanseo Park, Woo-Rham Bae, Jinhyung Lee, Jeongho Hwang, Deog-Kyoon Jeong:
A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. IEEE J. Solid State Circuits 53(10): 2982-2993 (2018) - [j79]Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 436-440 (2018) - [j78]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong:
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2691-2702 (2018) - [j77]Jinhyung Lee, Kwanseo Park, Kwangho Lee, Deog-Kyoon Jeong:
A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1295-1299 (2018) - [j76]Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018) - [j75]Young-Ha Hwang, Jun-Eun Park, Yoonho Song, Deog-Kyoon Jeong:
A 20 k-to-100kS/s Sub-µW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-µm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1814-1818 (2018) - [j74]Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1819-1823 (2018) - [j73]Hong-Seok Choi, Jeongho Hwang, Gyu-Seob Jeong, Gyungock Kim, Deog-Kyoon Jeong:
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1824-1828 (2018) - [j72]Mino Kim, Joo-Hyung Chae, Sungphil Choi, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong, Suhwan Kim:
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1894-1898 (2018) - [j71]Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong:
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. 65(7): 5979-5989 (2018) - [c50]Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. A-SSCC 2018: 73-76 - [c49]Young-Ha Hwang, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong:
A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS. A-SSCC 2018: 247-248 - [c48]Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong:
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. BCICTS 2018: 263-266 - [c47]Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong:
Adiabatically driven touch controller analog front-end for ultra-thin displays. CICC 2018: 1-4 - [c46]Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Seong Ho Park, Deog-Kyoon Jeong:
4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS. ISLPED 2018: 11:1-11:6 - [c45]Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS. VLSI Circuits 2018: 51-52 - [c44]Jun-Eun Park, Deog-Kyoon Jeong:
A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit. VLSI Circuits 2018: 231-232 - 2017
- [j70]Deog-Kyoon Jeong, Jaeha Kim:
Introduction to the Special Section on the 2016 Asian Solid-State Circuits Conference (A-SSCC 2016). IEEE J. Solid State Circuits 52(10): 2521-2522 (2017) - [j69]Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong:
Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection. Sensors 17(9): 1962 (2017) - [j68]Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 655-659 (2017) - [j67]Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong:
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1377-1381 (2017) - [j66]Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong:
A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1417-1421 (2017) - [j65]Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong:
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1432-1436 (2017) - [j64]Woo-Rham Bae, Borivoje Nikolic, Deog-Kyoon Jeong:
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3543-3547 (2017) - [c43]Young-Ha Hwang, Jun-Eun Park, Deog-Kyoon Jeong:
A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications. A-SSCC 2017: 293-296 - [c42]Kwanseo Park, Woo-Rham Bae, Deog-Kyoon Jeong:
A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. CICC 2017: 1-4 - [c41]Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong:
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC 2017: 494-495 - 2016
- [j63]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. IEEE J. Solid State Circuits 51(10): 2312-2327 (2016) - [j62]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. IEEE J. Solid State Circuits 51(10): 2357-2367 (2016) - [j61]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1393-1403 (2016) - [j60]Yoonsoo Kim, Gyu-Seob Jeong, Jun-Eun Park, Joonbae Park, Gyungock Kim, Deog-Kyoon Jeong:
20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1034-1038 (2016) - [j59]Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1106-1110 (2016) - [j58]Woo-Rham Bae, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog-Kyoon Jeong:
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2234-2243 (2016) - [c40]Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong:
A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. A-SSCC 2016: 241-244 - [c39]Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong:
A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS 2016: 1662-1665 - [c38]Haram Ju, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. ISCAS 2016: 2346-2349 - [c37]Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS. ISCAS 2016: 2906 - [c36]Jun-Eun Park, Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Deog-Kyoon Jeong:
11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp. ISSCC 2016: 210-211 - 2015
- [j57]Woo-Rham Bae, Deog-Kyoon Jeong:
A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances. Int. J. Circuit Theory Appl. 43(12): 2057-2071 (2015) - [j56]Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50(11): 2603-2612 (2015) - [j55]Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. IEEE Trans. Circuits Syst. II Express Briefs 62-II(9): 836-840 (2015) - [c35]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. A-SSCC 2015: 1-4 - [c34]Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim:
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. A-SSCC 2015: 1-4 - [c33]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC 2015: 1-4 - [c32]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong:
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC 2015: 384-387 - [c31]Woo-Rham Bae, Chang-Soo Yoon, Deog-Kyoon Jeong:
A low-power pulse position modulation transceiver. ISCAS 2015: 1614-1617 - [c30]Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. ISCAS 2015: 2389-2392 - [c29]Sungwoo Kim, Sungchun Jang, Jun-Eun Park, Yoonsoo Kim, Gyungock Kim, Deog-Kyoon Jeong:
A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop. ISCAS 2015: 2856-2859 - [c28]Jun-Eun Park, Yoonsoo Kim, Sungwoo Kim, Gyungock Kim, Deog-Kyoon Jeong:
20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS. ISCAS 2015: 2864-2867 - [c27]Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. VLSIC 2015: 136- - 2014
- [j54]Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong:
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. IEEE J. Solid State Circuits 49(3): 657-672 (2014) - [j53]Jun-Eun Park, Dong-Hyuk Lim, Deog-Kyoon Jeong:
A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels. IEEE J. Solid State Circuits 49(10): 2305-2318 (2014) - [j52]Taeho Kim, Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Jiheon Park, Deog-Kyoon Jeong:
A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(5): 304-308 (2014) - [j51]Jong-Kwan Woo, Hyunjoong Lee, Hwi-Cheol Kim, Deog-Kyoon Jeong, Suhwan Kim:
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 585-592 (2014) - [j50]Byoung-Joo Yoo, Woo-Rham Bae, Jiho Han, Jaeha Kim, Deog-Kyoon Jeong:
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1226-1237 (2014) - [c26]Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. A-SSCC 2014: 101-104 - [c25]Woo-Rham Bae, Deog-Kyoon Jeong, Byoung-Joo Yoo:
A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. DDECS 2014: 55-58 - [c24]Woo-Rham Bae, Deog-Kyoon Jeong:
A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth. ICEIC 2014: 1-2 - [c23]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014: 447-450 - [c22]Gyu-Seob Jeong, Hankyu Chi, Kyungock Kim, Deog-Kyoon Jeong:
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS. ISCAS 2014: 1492-1495 - [c21]Yoonsoo Kim, Woo-Rham Bae, Deog-Kyoon Jeong:
A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS. ISCAS 2014: 1869-1872 - 2013
- [j49]Daeyong Shim, Hyunsik Jeong, Hyunjoong Lee, Cyuyeol Rhee, Deog-Kyoon Jeong, Suhwan Kim:
A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM. IEEE J. Solid State Circuits 48(10): 2550-2557 (2013) - [c20]Dong-Wook Kim, Hankyu Chi, Yu-Sang Chun, Myung-Heon Chin, Gyungock Kim, Deog-Kyoon Jeong:
12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS. ISCAS 2013: 1115-1118 - [c19]Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. ISSCC 2013: 250-251 - 2012
- [c18]Dong-Hyuk Lim, Jun-Eun Park, Deog-Kyoon Jeong:
A low-noise differential front-end and its controller for capacitive touch screen panels. ESSCIRC 2012: 237-240 - [c17]Jaeha Kim, Sigang Ryu, Byoung-Joo Yoo, Hanseok Kim, Yunju Choi, Deog-Kyoon Jeong:
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs. ISCAS 2012: 754-757 - [c16]Woo-Rham Bae, Byoung-Joo Yoo, Deog-Kyoon Jeong:
Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface. ISOCC 2012: 49-52 - [c15]Taeho Kim, Deog-Kyoon Jeong:
A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology. ISOCC 2012: 53-56 - 2011
- [j48]Heesoo Song, Deok-Soo Kim, Do-Hwan Oh, Suhwan Kim, Deog-Kyoon Jeong:
A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. IEEE J. Solid State Circuits 46(2): 424-434 (2011) - [j47]Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong:
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits 46(11): 2560-2570 (2011) - [j46]Yohwan Yoon, Deog-Kyoon Jeong:
A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1264-1276 (2011) - [j45]Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim:
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 494-498 (2011) - [c14]Sungchun Jang, Heesoo Song, Seokmin Ye, Deog-Kyoon Jeong:
A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit. ISSCC 2011: 450-452 - [c13]Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jaeduk Han, Sunkwon Kim, Kyu-Sang Park, Dong-Hyuk Lim, Jung-Hoon Chun, Deog-Kyoon Jeong, Suhwan Kim:
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. ISSCC 2011: 494-496 - 2010
- [j44]Deok-Soo Kim, Heesoo Song, Taeho Kim, Suhwan Kim, Deog-Kyoon Jeong:
A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller. IEEE J. Solid State Circuits 45(11): 2300-2311 (2010) - [j43]Jiho Han, Deog-Kyoon Jeong:
A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems. IEEE Trans. Instrum. Meas. 59(2): 433-439 (2010) - [c12]Jiho Han, Hankyu Chi, Deog-Kyoon Jeong:
A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment. ISCAS 2010: 193-196
2000 – 2009
- 2009
- [j42]Jiho Han, Deog-Kyoon Jeong:
Practical considerations in the design and implementation of time synchronization systems using IEEE 1588. IEEE Commun. Mag. 47(11): 164-170 (2009) - [j41]Jeong-Kyoum Kim, Jaeha Kim, Gyudong Kim, Deog-Kyoon Jeong:
A Fully Integrated 0.13-µm CMOS 40-Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 44(5): 1510-1521 (2009) - [j40]Young-Deok Kim, Hyun-Seok Ahn, Suhwan Kim, Deog-Kyoon Jeong:
A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(6): 1221-1230 (2009) - [j39]Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Deog-Kyoon Jeong:
Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(12): 2544-2555 (2009) - [j38]Jong-Kwan Woo, Dong-Yong Shin, Deog-Kyoon Jeong, Suhwan Kim:
High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer. IEEE Trans. Consumer Electron. 55(3): 1431-1438 (2009) - [c11]Nan Xing, Heesoo Song, Deog-Kyoon Jeong, Suhwan Kim:
A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines. SoCC 2009: 43-46 - 2008
- [j37]Jonghoon Lee, Chul-Ki Lee, Jiho Han, Hanku Chi, Taesik Na, Deog-Kyoon Jeong, Jae-Hwa Kwak, Jin-su Ahn, Sangho Yoon:
An ethernet switch architecture for bandwidth provision of broadband access networks. IEEE Commun. Mag. 46(4): 160-167 (2008) - [j36]Byoung-Mo Moon, Young-June Park, Deog-Kyoon Jeong:
Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 1036-1040 (2008) - [c10]Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim:
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. ICCAD 2008: 169-172 - 2007
- [j35]Chul-Ki Lee, Jae-Hwa Kwak, Deog-Kyoon Jeong:
Enhanced token bucket policer using reduced fair queuing for Ethernet access networks. IET Commun. 1(6): 1248-1255 (2007) - [j34]Chul Ki Lee, Deog-Kyoon Jeong, Yong Chul Shim:
Virtual minimum potential queuing. J. High Speed Networks 16(4): 323-339 (2007) - [j33]Hoesam Jeong, Byoung-Joo Yoo, Cheol Kyu Han, Sang-Yoon Lee, Kang-Yoon Lee, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture. IEEE J. Solid State Circuits 42(6): 1318-1327 (2007) - [j32]Won-Jun Choe, Bong-Joon Lee, Jaeha Kim, Deog-Kyoon Jeong, Gyudong Kim:
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme. IEEE J. Solid State Circuits 42(9): 2012-2020 (2007) - [c9]Do-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO. ISSCC 2007: 222-598 - 2006
- [j31]Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Namhoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS. IEEE J. Solid State Circuits 41(4): 899-908 (2006) - [j30]Hwi-Cheol Kim, Deog-Kyoon Jeong, Wonchan Kim:
A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(4): 795-801 (2006) - [c8]Young-Deok Kim, Hyun-Seok Ahn, Joon-Young Park, Suhwan Kim, Deog-Kyoon Jeong:
A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification. ISSCC 2006: 587-596 - [c7]Hyung-Rok Lee, Ook Kim, Keewook Jung, John Shin, Deog-Kyoon Jeong:
A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm. ISSCC 2006: 2402-2411 - 2005
- [j29]Hankyu Lim, Deog-Kyoon Jeong, KyungTae Kim, JunMo Park, Han-Gyoo Kim:
A single-chip storage LSI for home networks. IEEE Commun. Mag. 43(5): 141-148 (2005) - [j28]Hyung-Rok Lee, Moon-Sang Hwang, Bong-Joon Lee, Young-Deok Kim, Dohwan Oh, Jaeha Kim, Sang-Hyun Lee, Deog-Kyoon Jeong, Wonchan Kim:
A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique. IEEE J. Solid State Circuits 40(11): 2148-2158 (2005) - [j27]Hyungki Huh, Yido Koo, Kang-Yoon Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. IEEE J. Solid State Circuits 40(11): 2228-2236 (2005) - 2004
- [j26]Jong-Sang Choi, Moon-Sang Hwang, Deog-Kyoon Jeong:
A 0.18-μm CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method. IEEE J. Solid State Circuits 39(3): 419-425 (2004) - [j25]Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong:
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. IEEE J. Solid State Circuits 39(5): 795-803 (2004) - [j24]Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Soo-Ik Chae, W. Kim:
A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b. IEEE J. Solid State Circuits 39(7): 1185-1190 (2004) - 2003
- [j23]Jaeha Kim, Deog-Kyoon Jeong:
Multi-gigabit-rate clock and data recovery based on blind oversampling. IEEE Commun. Mag. 41(12): 68-74 (2003) - [j22]Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. IEEE J. Solid State Circuits 38(1): 43-53 (2003) - [j21]Bong-Joon Lee, Moon-Sang Hwang, Sang-Hyun Lee, Deog-Kyoon Jeong:
A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization. IEEE J. Solid State Circuits 38(11): 1821-1829 (2003) - [j20]Youngdon Choi, Deog-Kyoon Jeong, Wontae Kim:
Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 775-783 (2003) - [c6]Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Wonchan Kim:
A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b. ESSCIRC 2003: 225-228 - 2002
- [j19]Yido Koo, Hyungki Huh, Yongsik Cho, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems. IEEE J. Solid State Circuits 37(5): 536-542 (2002) - [j18]Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn:
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. IEEE J. Solid State Circuits 37(12): 1822-1830 (2002) - 2001
- [j17]Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Wonchan Kim:
A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique. IEEE J. Solid State Circuits 36(5): 800-809 (2001) - [j16]Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn:
A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. IEEE J. Solid State Circuits 36(12): 1974-1983 (2001) - 2000
- [j15]Jong-Seok Kim, Deog-Kyoon Jeong, Gyudong Kim:
A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers. IEEE J. Solid State Circuits 35(1): 74-84 (2000) - [j14]Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE J. Solid State Circuits 35(3): 377-384 (2000) - [j13]Gijung Ahn, Deog-Kyoon Jeong, Gyudong Kim:
A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission. IEEE J. Solid State Circuits 35(6): 915-918 (2000)
1990 – 1999
- 1999
- [c5]Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. CICC 1999: 299-302 - 1998
- [j12]Yong Moon, Deog-Kyoon Jeong:
A 32×32-b adiabatic register file with supply clock generator. IEEE J. Solid State Circuits 33(5): 696-701 (1998) - [j11]Kyeongho Lee, Yeshik Shin, Sungjoon Kim, Deog-Kyoon Jeong, Gyudong Kim, Bruce Kim, Victor Da Costa:
1.04 GBd low EMI digital video interface system using small swing serial link technique. IEEE J. Solid State Circuits 33(5): 816-823 (1998) - [c4]Yeshik Shin, Jin-su Ahn, Hyung-Rok Lee, Deog-Kyoon Jeong:
Design and Implementation of OTCA MAC Protocol for High-Speed Point-to-Point Ring Network. LCN 1998: 345-352 - 1997
- [j10]Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim:
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. IEEE J. Solid State Circuits 32(5): 691-700 (1997) - 1996
- [j9]Yong Moon, Deog-Kyoon Jeong:
An efficient charge recovery logic circuit. IEEE J. Solid State Circuits 31(4): 514-522 (1996) - 1995
- [j8]Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong:
A CMOS serial link for fully duplexed data communication. IEEE J. Solid State Circuits 30(4): 353-364 (1995) - [j7]Daejeong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. IEEE J. Solid State Circuits 30(8): 940-943 (1995) - [c3]Jesung Kim, Sang Lyul Min, Sanghoon Jeon, ByoungChul Ahn, Deog-Kyoon Jeong, Chong-Sang Kim:
U-Cache: A Cost-Effective Solution to the Synonym Problem. HPCA 1995: 243-252 - 1994
- [c2]Deog-Kyoon Jeong, David D. Lee, J. Duane Northcutt, Andreas von Bechtolsheim, David R. Ditzel, Amnon Fisher:
Hotpads - macro-dells for gigabit I/O. Hot Interconnects 1994: 249-257 - [c1]Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. ISCAS 1994: 319-322 - 1993
- [j6]Seong Baeg Kim, Myung Soon Park, Sun-Ho Park, Sang Lyul Min, Heonshik Shin, Chong-Sang Kim, Deog-Kyoon Jeong:
Threaded prefetching: An adaptive instruction prefetch mechanism. Microprocess. Microprogramming 39(1): 1-15 (1993) - [j5]Joongsik Kih, Byungsoo Chang, Deog-Kyoon Jeong:
Class-AB large-swing CMOS buffer amplifier with controlled bias current. IEEE J. Solid State Circuits 28(12): 1350-1353 (1993) - [j4]Sang Lyul Min, Jesung Kim, Chong-Sang Kim, Heonshik Shin, Deog-Kyoon Jeong:
V-P cache: a storage efficient virtual cache organization. Microprocess. Microsystems 17(9): 537-546 (1993) - 1992
- [j3]Gregory A. Uvieghara, Wen-mei W. Hwu, Yoshinobu Nakagome, Deog-Kyoon Jeong, David D. Lee, David A. Hodges, Yale N. Patt:
An experimental single-chip data flow CPU. IEEE J. Solid State Circuits 27(1): 17-28 (1992) - 1990
- [j2]Gregory A. Uvieghara, Yoshinobu Nakagome, Deog-Kyoon Jeong, David A. Hodges:
An on-chip smart memory for a data-flow CPU. IEEE J. Solid State Circuits 25(1): 84-94 (1990)
1980 – 1989
- 1989
- [j1]Deog-Kyoon Jeong, David A. Wood, Garth A. Gibson, Susan J. Eggers, David A. Hodges, Randy H. Katz, David A. Patterson:
A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller. IEEE J. Solid State Circuits 24(6): 1699-1707 (1989)
Coauthor Index
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