default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDPhilip Brisk
Person information
- affiliation: University of California, Riverside, Department of Computer Sience and Engineering, CA, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[i1]Shane Hoang, Mabel Shehada, Zinal Patel, Minh-Huy Tran, Konstantinos Karydis, Philip Brisk, William H. Grover:
Error detection using pneumatic logic. CoRR abs/2401.16500 (2024)- 2023
- [j41]Amin Kalantar
, Zachary Zimmerman, Philip Brisk:
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge. ACM Trans. Reconfigurable Technol. Syst. 16(1): 12:1-12:27 (2023) - [c101]Tyson Loveless, Philip Brisk:
Compiling Functions onto Digital Microfluidics. CGO 2023: 136-148 - [c100]Prithviraj Yuvaraj, Amin Akalantar, Eamonn J. Keogh, Philip Brisk:
Feature Extraction Accelerator for Streaming Time Series. FCCM 2023: 207 - 2022
- [p2]Philip Brisk, Fabrice Rastello:
Properties and Flavours. SSA-based Compiler Design 2022: 13-22 - [p1]Pedro C. Diniz, Philip Brisk:
Hardware Compilation Using SSA. SSA-based Compiler Design 2022: 329-345 - 2021
- [j40]Jason Ott, Tyson Loveless, Christopher Curtis, Mohsen Lesani, Philip Brisk:
BioScript: programming safe chemistry on laboratories-on-a-chip. Commun. ACM 64(2): 97-104 (2021) - [j39]Joshua Potter, William H. Grover, Philip Brisk:
Dynamic Radial Placement and Routing in Paper Microfluidics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 1971-1984 (2021) - [j38]Brian Crites, Cody Falzone, Tristan Lopez, Karen Kong, Philip Brisk:
Reducing Microfluidic Very Large-Scale Integration (mVLSI) Chip Area by Seam Carving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2104-2116 (2021) - [c99]Maryam Shahcheraghi, Trevor Cappon, Samet Oymak, Evangelos E. Papalexakis, Eamonn J. Keogh, Zachary Zimmerman, Philip Brisk:
Matrix Profile Index Approximation for Streaming Time Series. IEEE BigData 2021: 2775-2784 - [c98]Amin Kalantar, Zachary Zimmerman, Philip Brisk:
FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction. FCCM 2021: 40-49 - [c97]Tyson Loveless, Jason Ott, Philip Brisk:
Time- and resource-constrained scheduling for digital microfluidic biochips. ICCPS 2021: 198-208 - 2020
- [j37]Jason Ott, Daniel Tan, Tyson Loveless, William H. Grover, Philip Brisk:
ChemStor: Using Formal Methods To Guarantee Safe Storage and Disposal of Chemicals. J. Chem. Inf. Model. 60(7): 3416-3422 (2020) - [j36]Brian Crites, Karen Kong, Philip Brisk:
Directed Placement for mVLSI Devices. ACM J. Emerg. Technol. Comput. Syst. 16(2): 14:1-14:26 (2020) - [c96]Tyson Loveless, Jason Ott, Philip Brisk:
A performance-optimizing compiler for cyber-physical digital microfluidic biochips. CGO 2020: 171-184 - [c95]Sina Faezi, Sujit Rokka Chhetri, Arnav Vaibhav Malawade, John Charles Chaput, William H. Grover, Philip Brisk, Mohammad Abdullah Al Faruque:
Acoustic Side Channel Attack Against DNA Synthesis Machines: Poster Abstract. ICCPS 2020: 186-187 - [c94]Hugo Brunie, Costin Iancu, Khaled Z. Ibrahim, Philip Brisk, Brandon Cook:
Tuning floating-point precision using dynamic program information and temporal locality. SC 2020: 50 - [c93]Frédéric Gessler, Philip Brisk, Mirjana Stojilovic:
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. VLSID 2020: 78-83
2010 – 2019
- 2019
- [j35]Philip Brisk, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatié, Swaroop Ghosh, Xun Jiao:
TCAD EIC Message: February 2019. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 197-198 (2019) - [j34]Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky:
Hardware-Assisted Cross-Generation Prediction of GPUs Under Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1133-1146 (2019) - [c92]Zachary Zimmerman, Kaveh Kamgar, Nader Shakibay Senobari, Brian Crites, Gareth J. Funning, Philip Brisk, Eamonn J. Keogh:
Matrix Profile XIV: Scaling Time Series Motif Discovery with GPUs to Break a Quintillion Pairwise Comparisons a Day and Beyond. SoCC 2019: 74-86 - [c91]Radhakrishna Sanka, Brian Crites, Jeffrey McDaniel, Philip Brisk, Douglas Densmore:
Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper. ICCAD 2019: 1-8 - [c90]Zachary Zimmerman, Nader Shakibay Senobari, Gareth J. Funning, Evangelos E. Papalexakis, Samet Oymak, Philip Brisk, Eamonn J. Keogh:
Matrix Profile XVIII: Time Series Mining in the Face of Fast Moving Streams using a Learned Approximate Matrix Profile. ICDM 2019: 936-945 - [c89]Sina Faezi, Sujit Rokka Chhetri, Arnav Vaibhav Malawade, John Charles Chaput, William H. Grover, Philip Brisk, Mohammad Abdullah Al Faruque:
Oligo-Snoop: A Non-Invasive Side Channel Attack Against DNA Synthesis Machines. NDSS 2019 - [c88]Sina Boroumand, Philip Brisk:
Approximate Adder Tree Synthesis for FPGAs. ReConFig 2019: 1-8 - 2018
- [j33]Kenneth O'Neal, Daniel T. Grissom, Philip Brisk:
Resource-Constrained Scheduling for Digital Microfluidic Biochips. ACM J. Emerg. Technol. Comput. Syst. 14(1): 7:1-7:26 (2018) - [j32]Yan Zhu, Zachary Zimmerman, Nader Shakibay Senobari, Chin-Chia Michael Yeh, Gareth J. Funning, Abdullah Mueen, Philip Brisk, Eamonn J. Keogh:
Exploiting a novel algorithm and GPUs to break the ten quadrillion pairwise comparisons barrier for time series motifs and joins. Knowl. Inf. Syst. 54(1): 203-236 (2018) - [j31]Alireza Abdoli, Philip Brisk:
Stationary-Mixing Field-Programmable Pin-Constrained Digital Microfluidic Biochip. Microelectron. J. 77: 34-48 (2018) - [j30]Jason Ott, Tyson Loveless, Christopher Curtis, Mohsen Lesani, Philip Brisk:
BioScript: programming safe chemistry on laboratories-on-a-chip. Proc. ACM Program. Lang. 2(OOPSLA): 128:1-128:31 (2018) - [j29]Wajid Hassan Minhass, Jeffrey McDaniel, Michael Lander Raagaard, Philip Brisk, Paul Pop, Jan Madsen:
Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 615-628 (2018) - [c87]Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi:
Exploration of approximate multipliers design space using carry propagation free compressors. ASP-DAC 2018: 611-616 - [c86]Christopher Curtis, Daniel T. Grissom, Philip Brisk:
A compiler for cyber-physical digital microfluidic biochips. CGO 2018: 365-377 - [c85]Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk:
Approximate quaternary addition with the fast carry chains of FPGAs. DATE 2018: 577-580 - [c84]Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk:
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. FPL 2018: 21-25 - [c83]Kenneth O'Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard, Philip Brisk:
HLSPredict: cross platform performance prediction for FPGA high-level synthesis. ICCAD 2018: 104 - [c82]Brian Crites, Radhakrishna Sanka, Joshua Lippai, Jeffrey McDaniel, Philip Brisk, Douglas Densmore:
ParchMint: A Microfluidics Benchmark Suite. IISWC 2018: 78-79 - [c81]Junchao Wang, Lingxuan Fu, Liyang Yu, Xiwei Huang, Philip Brisk, William H. Grover:
Accelerating Simulation of Particle Trajectories in Microfluidic Devices by Constructing a Cloud Database. ISVLSI 2018: 666-671 - [c80]Kenneth O'Neal, Philip Brisk:
Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey. ISVLSI 2018: 763-768 - 2017
- [j28]Skyler Windh, Calvin Phung, Daniel T. Grissom, Paul Pop, Philip Brisk:
Performance Improvements and Congestion Reduction for Routing-Based Synthesis for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 41-54 (2017) - [j27]Jeffrey McDaniel, Zachary Zimmerman, Daniel T. Grissom, Philip Brisk:
PCB Escape Routing and Layer Minimization for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 69-82 (2017) - [j26]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16(5s): 125:1-125:19 (2017) - [j25]Brian Crites, Karen Kong, Philip Brisk:
Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips. ACM Trans. Embed. Comput. Syst. 16(5s): 126:1-126:18 (2017) - [j24]Kenneth O'Neal, Philip Brisk, Ahmed Abousamra, Zack Waters, Emily Shriver:
GPU Performance Estimation using Software Rasterization and Machine Learning. ACM Trans. Embed. Comput. Syst. 16(5s): 148:1-148:21 (2017) - [c79]Lana Josipovic, Philip Brisk, Paolo Ienne:
From C to elastic circuits. ACSSC 2017: 121-125 - [c78]Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne:
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC 2017: 5:1-5:6 - [c77]Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky:
HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs. DAC 2017: 80:1-80:6 - [c76]Jeffrey McDaniel, William H. Grover, Philip Brisk:
The case for semi-automated design of microfluidic very large scale integration (mVLSI) chips. DATE 2017: 1793-1798 - [c75]Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi:
CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. DFT 2017: 1-6 - [c74]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM 2017: 134 - [c73]Joshua Potter, William H. Grover, Philip Brisk:
Design Automation for Paper Microfluidics with Passive Flow Substrates. ACM Great Lakes Symposium on VLSI 2017: 215-220 - [c72]Brian Crites, Karen Kong, Philip Brisk:
Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving. ACM Great Lakes Symposium on VLSI 2017: 459-462 - 2016
- [c71]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. FPL 2016: 1 - [c70]Yan Zhu, Zachary Zimmerman, Nader Shakibay Senobari, Chin-Chia Michael Yeh, Gareth J. Funning, Abdullah Mueen, Philip Brisk, Eamonn J. Keogh:
Matrix Profile II: Exploiting a Novel Algorithm and GPUs to Break the One Hundred Million Barrier for Time Series Motifs and Joins. ICDM 2016: 739-748 - [e2]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - 2015
- [j23]Jeffrey McDaniel, Brian Crites, Philip Brisk, William H. Grover:
Flow-Layer Physical Design for Microchips Based on Monolithic Membrane Valves. IEEE Des. Test 32(6): 51-59 (2015) - [j22]Daniel T. Grissom, Christopher Curtis, Skyler Windh, Calvin Phung, Navin Kumar, Zachary Zimmerman, Kenneth O'Neal, Jeffrey McDaniel, Nick Liao, Philip Brisk:
An open-source compiler and PCB synthesis tool for digital microfluidic biochips. Integr. 51: 169-193 (2015) - [j21]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers 64(2): 329-341 (2015) - [j20]Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk:
Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1928-1941 (2015) - [j19]Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk:
Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation. ACM Trans. Reconfigurable Technol. Syst. 7(4): 37:1-37:22 (2015) - [c69]Christopher Jaress, Philip Brisk, Daniel T. Grissom:
Rapid online fault recovery for cyber-physical digital microfluidic biochips. VTS 2015: 1-6 - 2014
- [j18]Daniel T. Grissom, Christopher Curtis, Philip Brisk:
Interpreting Assays with Control Flow on Digital Microfluidic Biochips. ACM J. Emerg. Technol. Comput. Syst. 10(3): 24:1-24:30 (2014) - [j17]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. 11(2): 15:1-15:26 (2014) - [j16]Daniel T. Grissom, Philip Brisk:
Fast Online Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 356-369 (2014) - [j15]Daniel T. Grissom, Jeffrey McDaniel, Philip Brisk:
A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1657-1670 (2014) - [j14]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 62-75 (2014) - [c68]Joseph Tarango, Eamonn J. Keogh, Philip Brisk:
Accelerating the dynamic time warping distance measure using logarithmetic arithmetic. ACSSC 2014: 404-408 - [c67]Johnathan Fiske, Daniel T. Grissom, Philip Brisk:
Exploring speed and energy tradeoffs in droplet transport for digital microfluidic biochips. ASP-DAC 2014: 231-237 - [c66]Yehdhih Ould Mohammed Moctar, Philip Brisk:
Parallel FPGA Routing based on the Operator Formulation. DAC 2014: 193:1-193:6 - [c65]Daniel T. Grissom, Jeffrey McDaniel, Philip Brisk:
Performance and cost analysis of NoC-inspired virtual topologies for digital microfluidic biochips. ISIC 2014: 352-355 - [c64]Jeffrey McDaniel, Daniel T. Grissom, Philip Brisk:
Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestion. VLSI-SoC 2014: 1-6 - [c63]Jeffrey McDaniel, Brendon Parker, Philip Brisk:
Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips. VLSI-SoC 2014: 1-6 - 2013
- [j13]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 681-694 (2013) - [j12]Philip Brisk, Tulika Mitra:
Introduction to the special issue on application-specific processors. ACM Trans. Embed. Comput. Syst. 13(2): 15:1-15:3 (2013) - [c62]Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, Philip Brisk:
Design and verification tools for continuous fluid flow-based microfluidic devices. ASP-DAC 2013: 219-224 - [c61]Jeffrey McDaniel, Christopher Curtis, Philip Brisk:
Automatic synthesis of microfluidic large scale integration chips from a domain-specific language. BioCAS 2013: 101-104 - [c60]Joseph Tarango, Eamonn J. Keogh, Philip Brisk:
Instruction set extensions for Dynamic Time Warping. CODES+ISSS 2013: 18:1-18:10 - [c59]Daniel T. Grissom, Philip Brisk:
A field-programmable pin-constrained digital microfluidic biochip. DAC 2013: 46:1-46:9 - [c58]Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne:
An EDA-friendly protection scheme against side-channel attacks. DATE 2013: 410-415 - [c57]Sambit Kumar Shukla, Yang Yang, Laxmi N. Bhuyan, Philip Brisk:
Shared memory heterogeneous computation on PCIe-supported platforms. FPL 2013: 1-4 - [c56]Liang Chen, Joseph Tarango, Tulika Mitra, Philip Brisk:
A just-in-time customizable processor. ICCAD 2013: 524-531 - [e1]Philip Brisk, José Gabriel F. Coutinho, Pedro C. Diniz:
Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings. Lecture Notes in Computer Science 7806, Springer 2013, ISBN 978-3-642-36811-0 [contents] - 2012
- [j11]Benoit Boissinot, Philip Brisk, Alain Darte, Fabrice Rastello:
SSI Properties Revisited. ACM Trans. Embed. Comput. Syst. 11(S1): 21 (2012) - [c55]Daniel T. Grissom, Philip Brisk:
Fast online synthesis of generally programmable digital microfluidic biochips. CODES+ISSS 2012: 413-422 - [c54]Daniel T. Grissom, Philip Brisk:
Path scheduling on digital microfluidic biochips. DAC 2012: 26-35 - [c53]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548 - [c52]Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk:
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264 - [c51]Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk:
Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. FPL 2012: 91-98 - [c50]Daniel T. Grissom, Philip Brisk:
A high-performance online assay interpreter for digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2012: 103-106 - [c49]Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Counting stream registers: An efficient and effective snoop filter architecture. ICSAMOS 2012: 120-127 - [c48]Kenneth O'Neal, Daniel T. Grissom, Philip Brisk:
Force-Directed List Scheduling for Digital Microfluidic Biochips. VLSI-SoC 2012: 7-11 - [c47]Daniel T. Grissom, Kenneth O'Neal, Benjamin Preciado, Hiral Patel, Robert Doherty, Nick Liao, Philip Brisk:
A digital microfluidic biochip synthesis framework. VLSI-SoC 2012: 177-182 - 2011
- [j10]Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne:
Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4(4): 39:1-39:19 (2011) - [c46]Philip Brisk:
Architecture and design automation for application-specific processors. ASICON 2011: 1094-1097 - [c45]Quentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, Fabrice Rastello:
Graph-coloring and treescan register allocation using repairing. CASES 2011: 45-54 - [c44]Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
A first step towards automatic application of power analysis countermeasures. DAC 2011: 230-235 - [c43]Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne:
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246 - 2010
- [j9]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 341-354 (2010) - [j8]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1096-1109 (2010) - [j7]Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 578-590 (2010) - [c42]Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712 - [c41]Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24 - [c40]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC 2010: 126-140
2000 – 2009
- 2009
- [j6]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. 13(1-2): 115-137 (2009) - [j5]Ani Nahapetian, Philip Brisk, Soheil Ghiasi, Majid Sarrafzadeh:
An approximation algorithm for scheduling on heterogeneous reconfigurable resources. ACM Trans. Embed. Comput. Syst. 9(1): 5:1-5:20 (2009) - [j4]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [j3]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. 2(3): 19:1-19:42 (2009) - [c39]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic 2009: 213-218 - [c38]Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209 - [c37]Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219 - [c36]Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36 - [c35]José Luis Ayala, David Atienza, Philip Brisk:
Thermal-aware data flow analysis. DAC 2009: 613-614 - [c34]Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270 - [c33]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. FPGA 2009: 286 - [c32]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL 2009: 242-249 - [c31]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510 - [c30]Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77 - [c29]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197 - [c28]Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD 2009: 689-696 - [c27]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD 2009: 797-804 - [c26]Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne:
Arithmetic optimization for custom instruction set synthesis. SASP 2009: 54-57 - [c25]Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne:
Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP 2009: 114-121 - [c24]Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS 2009: 115-120 - 2008
- [j2]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1761-1774 (2008) - [c23]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143 - [c22]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339 - [c21]Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Design space exploration for field programmable compressor trees. CASES 2008: 207-216 - [c20]Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248 - [c19]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255 - [c18]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261 - [c17]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180 - [c16]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - [c15]Jani Boutellier, Veeranjaneyulu Sadhanala, Christophe Lucarz, Philip Brisk, Marco Mattavelli:
Scheduling of dataflow models within the Reconfigurable Video Coding framework. SiPS 2008: 182-187 - 2007
- [c14]Tammara Massey, Philip Brisk, Foad Dabiri, Majid Sarrafzadeh:
Delay aware, reconfigurable security for embedded systems. BODYNETS 2007: 12 - [c13]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134 - [c12]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217 - [c11]Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337 - [c10]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409 - [c9]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179 - [c8]Philip Brisk, Majid Sarrafzadeh:
Interference graphs for procedures in static single information form are interval graphs. SCOPES 2007: 101-110 - 2006
- [j1]Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh:
Optimal register sharing for high-level synthesis of SSA form programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 772-779 (2006) - [c7]Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh:
Layout driven data communication optimization for high level synthesis. DATE 2006: 1185-1190 - 2005
- [c6]Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid Sarrafzadeh:
A dictionary construction technique for code compression systems with echo instructions. LCTES 2005: 105-114 - [c5]Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh:
Adaptive and fault tolerant medical vest for life-critical medical monitoring. SAC 2005: 272-279 - 2004
- [c4]Philip Brisk, Adam Kaplan, Majid Sarrafzadeh:
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. DAC 2004: 395-400 - [c3]Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh:
Instruction Selection for Compilers that Target Architectures with Echo Instructions. SCOPES 2004: 229-243 - 2003
- [c2]Adam Kaplan, Philip Brisk, Ryan Kastner:
Data communication estimation and reduction for reconfigurable systems. DAC 2003: 616-621 - 2002
- [c1]Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh:
Instruction generation and regularity extraction for reconfigurable processors. CASES 2002: 262-269
Coauthor Index
[j26] [c79] [c78] [c74] [c71] [e2] [j21] [j17] [j14] [j13] [c58] [c53] [c52] [c49] [j10] [c44] [c43] [j9] [j8] [j7] [c42] [c41] [c40] [j6] [j4] [j3] [c39] [c38] [c37] [c36] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [j2] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c13] [c12] [c11] [c10] [c9]
Zachary Schall-Zimmerman
aka: Zachary Zimmerman
aka: Zachary Zimmerman
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-09-09 00:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
