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2020 – today
- 2023
[j2]Stefano Ambrogio, Pritish Narayanan, Atsuya Okazaki
, Andrea Fasoli, Charles Mackin, Kohji Hosokawa, Akiyo Nomura, Takeo Yasuda, An Chen, Alexander M. Friz, Masatoshi Ishii, Jose Luquin, Yasuteru Kohda, Nicole Saulnier, Kevin Brew, Samuel Choi, Injo Ok, Timothy Philip, Victor Chan, Mary Claire Silvestre, Ishtiaq Ahsan, Vijay Narayanan, Hsinyu Tsai, Geoffrey W. Burr:
An analog-AI chip for energy-efficient speech recognition and transcription. Nat. 620(7975): 768-775 (2023)- [c8]Hsinyu Tsai, Pritish Narayanan, Shubham Jain, Stefano Ambrogio, Kohji Hosokawa, Masatoshi Ishii, Charles Mackin, Ching-Tzu Chen, Atsuya Okazaki, Akiyo Nomura, Irem Boybat, Ramachandran Muralidhar, Martin M. Frank, Takeo Yasuda, Alexander M. Friz, Yasuteru Kohda, An Chen, Andrea Fasoli, Malte J. Rasch, Stanislaw Wozniak, Jose Luquin, Vijay Narayanan, Geoffrey W. Burr:
Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). ISCAS 2023: 1-5 - [c7]Geoffrey W. Burr, Pritish Narayanan, Stefano Ambrogio, Atsuya Okazaki, Hsinyu Tsai, Kohji Hosokawa, Charles Mackin, Akiyo Nomura, Takeo Yasuda, J. Demarest, Kevin Brew, Victor Chan, Samuel Choi, T. Gordon, T. M. Levin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, An Chen, Andrea Fasoli, Jose Luquin, Nicole Saulnier, S. Teehan, Ishtiaq Ahsan, Vijay Narayanan:
Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). VLSI Technology and Circuits 2023: 1-2 - 2022
- [c6]Atsuya Okazaki, Pritish Narayanan, Stefano Ambrogio, Kohji Hosokawa, Hsinyu Tsai, Akiyo Nomura, Takeo Yasuda, Charles Mackin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, Katie Spoon, An Chen, Andrea Fasoli, Malte J. Rasch, Geoffrey W. Burr:
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers. ISCAS 2022: 3319-3323
2000 – 2009
- 2005
- [c5]Takeo Yasuda:
On-chip temperature sensor with high tolerance for process and temperature variation. ISCAS (2) 2005: 1024-1027 - 2003
- [c4]Takeo Yasuda, Kohji Hosokawa:
A low power CMOS circuit with Variable Souce Scheme (VSCMOS). ASP-DAC 2003: 404-407 - 2002
- [j1]Takeo Yasuda, Masaaki Yamamoto:
An On-Chip Power-on Reset Circuit for Low Voltage Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 366-372 (2002) - 2001
- [c3]Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera:
A dynamically phase adjusting PLL with a variable delay. ASP-DAC 2001: 275-280 - [c2]Takeo Yasuda, Masaaki Yamamoto, Takafumi Nishi:
A power-on reset pulse generator for low voltage applications. ISCAS (4) 2001: 599-601 - 2000
- [c1]Takeo Yasuda:
High-speed wide-locking range VCO with frequency calibration. ISCAS 2000: 45-48
Coauthor Index
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