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ORCIDShyamapada Mukherjee
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2020 – today
- 2023
[j8]Sharbani Purkayastha, Shyamapada Mukherjee:
PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing. Circuits Syst. Signal Process. 42(2): 801-827 (2023)- [j7]Sumanta Banerjee
, Shyamapada Mukherjee, Sivaji Bandyopadhyay, Partha Pakray:
An extract-then-abstract based method to generate disaster-news headlines using a DNN extractor followed by a transformer abstractor. Inf. Process. Manag. 60(3): 103291 (2023) - 2022
- [j6]Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee:
Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT. J. Circuits Syst. Comput. 31(9): 2250165:1-2250165:25 (2022) - [c9]Yagnyasenee Sen Gupta, Shyamapada Mukherjee:
A Reward-based Framework for Recovery and Utilization of Recyclable Wastes using Blockchain. OCIT 2022: 609-613 - 2020
- [j5]Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee:
Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology. J. Circuits Syst. Comput. 29(4): 2050057:1-2050057:22 (2020)
2010 – 2019
- 2019
- [j4]Prasun Datta, Shyamapada Mukherjee:
Architecture-aware routability-driven placer for large-scale mixed-size designs. IET Circuits Devices Syst. 13(8): 1209-1220 (2019) - [c8]Shyamapada Mukherjee, Neeraj Shivam, Astha Gangwal, Lokesh Khaitan, Amlan Jyoti Das:
Spoken Language Recognition Using CNN. ICIT 2019: 37-41 - [c7]Shyamapada Mukherjee, Kunal Chaudhary, Priya Jain, Bishal Paul:
Gait Recognition using Segmented Motion Flow Energy Image. ICCCNT 2019: 1-6 - 2018
- [c6]Prasun Datta, Shyamapada Mukherjee:
IPplacer: An Efficient 0-1 Integer Programming Based Placement for VLSI Circuits. ICCCNT 2018: 1-7 - [c5]Shyamapada Mukherjee, A. Nainwal, C. C. Das, Sharbani Purkayastha:
An Alternate Algorithmic Approach to FPGA Placement. ICCCNT 2018: 1-6 - 2017
- [j3]Shyamapada Mukherjee, Suchismita Roy:
Via-Aware Dogleg Routing Using Boolean Satisfiability. J. Circuits Syst. Comput. 26(4): 1750064:1-1750064:24 (2017) - [c4]Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee:
K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction. ISED 2017: 1-5 - [c3]Sharbani Purkayastha, Shyamapada Mukherjee:
Lookahead legalization based global placement for heterogeneous FPGAs. ISED 2017: 1-5 - 2016
- [j2]Shyamapada Mukherjee, Suchismita Roy:
Nearly-2-SAT Solutions for Segmented-Channel Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 128-140 (2016) - 2015
- [j1]Shyamapada Mukherjee, Suchismita Roy:
SAT based solutions for detailed routing of island style FPGA architectures. Microelectron. J. 46(8): 706-715 (2015) - [c2]Shyamapada Mukherjee, Suchismita Roy:
Multi terminal net routing for island style FPGAs using nearly-2-SAT computation. VDAT 2015: 1-6 - 2013
- [c1]Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy:
Congestion Balancing Global Router. VDAT 2013: 223-232
Coauthor Index
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