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2020 – today
- 2020
[j7]Yun-Ho Shin
, Seok-Jun Moon, Yong-Ju Kim, Ki-Yong Oh:
Vibration Control of Scanning Electron Microscopes with Experimental Approaches for Performance Enhancement. Sensors 20(8): 2277 (2020)
2010 – 2019
- 2015
- [c2]Sumin Choi, Heegon Kim, Daniel H. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yong-Ju Kim, Yunsaing Kim:
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC. 3DIC 2015: TS8.25.1-TS8.25.5 - 2014
- [j6]Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Yong-Ju Kim, Yunsaing Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 49(11): 2618-2630 (2014) - 2013
- [j5]Ji-Hoon Lim, Won-Young Jung, Yong-Ju Kim, Inchae Song, Jae-Kyung Wee:
A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique. IEICE Trans. Electron. 96-C(2): 277-284 (2013) - 2012
- [c1]Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim:
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. ISSCC 2012: 40-41 - 2011
- [j4]Young San Shin, Jae-Kyung Wee, Jong-Chan Ha, Ji-Hoon Lim, Yong-Ju Kim, Young-Sang Son:
A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. J. Circuits Syst. Comput. 20(4): 741-756 (2011)
2000 – 2009
- 2008
- [j3]Won-Young Jung, Hyungon Kim, Yong-Ju Kim, Jae-Kyung Wee:
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1177-1184 (2008) - 2007
- [j2]Ji-Hoon Lim, Jong-Chan Ha, Won-Young Jung, Yong-Ju Kim, Jae-Kyung Wee:
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. IEICE Trans. Electron. 90-C(3): 644-648 (2007) - 2006
- [j1]Yong-Ju Kim, Won-Young Jung, Jae-Kyung Wee:
Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards. IEICE Trans. Electron. 89-C(7): 1097-1105 (2006)
Coauthor Index
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