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ORCIDJavier Castro-Ramirez
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2010 – 2019
- 2014
[j2]Erica Tena-Sánchez
, Javier Castro-Ramirez, Antonio J. Acosta:
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(2): 203-215 (2014)- [c9]Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta:
Low-Power Differential Logic Gates for DPA Resistant Circuits. DSD 2014: 671-674 - [c8]Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta:
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. PATMOS 2014: 1-8 - 2013
- [j1]Piedad Brox, Javier Castro-Ramirez, Macarena C. Martínez-Rodríguez, Erica Tena, Carlos Jesús Jiménez-Fernández, Iluminada Baturone, Antonio J. Acosta:
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3182-3194 (2013) - 2012
- [c7]Macarena C. Martínez-Rodríguez, Piedad Brox, Javier Castro-Ramirez, Erica Tena, Antonio J. Acosta, Iluminada Baturone:
ASIC-in-the-loop methodology for verification of piecewise affine controllers. ICECS 2012: 388-391 - [c6]Susana Eiroa, Javier Castro-Ramirez, Macarena Cristina Martínez-Rodríguez, Erica Tena, Piedad Brox, Iluminada Baturone:
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification. ICECS 2012: 392-395 - 2010
- [c5]Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta:
Optimization of clock-gating structures for low-leakage high-performance applications. ISCAS 2010: 3220-3223
2000 – 2009
- 2009
- [c4]Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. PATMOS 2009: 76-85 - 2007
- [c3]Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta:
A switching noise vision of the optimization techniques for low-power synthesis. ECCTD 2007: 156-159 - [c2]Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta:
Asymmetric clock driver for improved power and noise performances. ISCAS 2007: 893-896 - 2006
- [c1]Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta:
Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS 2006: 439-449
Coauthor Index
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