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ORCIDAndrea Bonetti
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2020 – today
- 2022
[j9]Petar Jokic
, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini:
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. ACM Trans. Embed. Comput. Syst. 21(5): 56:1-56:36 (2022)- 2021
- [c14]Enric M. Calvo, Philippe Renevey, Mathieu Lemay, Andrea Bonetti, Marc Pons Solé, Régis Cattenoz, Stéphane Emery, Ricard Delgado-Gonzalo:
Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs. EMBC 2021: 6978-6981 - [i2]Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini:
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. CoRR abs/2106.12810 (2021) - 2020
- [j8]Benoît W. Denkinger, Flavio Ponzina, Soumya Basu, Andrea Bonetti, Szabolcs Balási, Martino Ruggiero, Miguel Peón Quirós, Davide Rossi, Andreas Burg, David Atienza:
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices. IEEE Des. Test 37(2): 84-92 (2020) - [j7]Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg:
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1207-1217 (2020) - [j6]Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg:
Gain-Cell Embedded DRAMs: Modeling and Design Space. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 646-659 (2020) - [c13]Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg:
Gain-Cell Embedded DRAMs: Modeling and Design Space. ISCAS 2020: 1 - [c12]Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman:
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. ISCAS 2020: 1
2010 – 2019
- 2019
- [j5]Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman:
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 2042-2046 (2019) - [c11]Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici:
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. A-SSCC 2019: 219-222 - [c10]Marco Widmer, Andrea Bonetti, Andreas Burg:
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems. DAC 2019: 36 - [c9]Ester Vicario Bravo, Andrea Bonetti, Andreas Burg:
Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space. ISCAS 2019: 1-5 - 2018
- [c8]Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg:
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. ISCAS 2018: 1-4 - 2017
- [j4]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg:
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 616-629 (2017) - [j3]Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg:
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2388-2400 (2017) - [j2]Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg:
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. ACM Trans. Design Autom. Electr. Syst. 22(4): 62:1-62:20 (2017) - [i1]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg:
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. CoRR abs/1708.09603 (2017) - 2016
- [j1]Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita:
An efficient tool for the assisted design of SAR ADCs capacitive DACs. Integr. 53: 88-99 (2016) - [c7]Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg:
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. ESSCIRC 2016: 261-264 - 2015
- [c6]Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita:
A tool for the assisted design of charge redistribution SAR ADCs. DATE 2015: 1265-1268 - [c5]Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg:
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. ISCAS 2015: 1426-1429 - [c4]Andrea Bonetti, Adam Teman, Andreas Burg:
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. ISCAS 2015: 1850-1853 - [c3]Stefano Brenna, Luca Bettini, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita:
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters. NORCAS 2015: 1-4 - 2014
- [c2]Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita:
A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs. MIPRO 2014: 74-79 - [c1]Stefano Brenna, Andrea Bonetti, Andrea L. Lacaita, Andrea Bonfanti:
A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs. UKSim 2014: 562-567
Coauthor Index
aka: Andreas Burg
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