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2020 – today
- 2024
[j39]Trong-Hung Nguyen
, Binh Kieu-Do-Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
High-Speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium. IEEE Access 12: 34918-34930 (2024)- [j38]Phuc-Phan Duong, Hieu Minh Nguyen, Ba-Anh Dao, Binh Kieu-Do-Nguyen, Thai-Ha Tran, Trong-Thuc Hoang, Cong-Kha Pham:
Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps. IEEE Access 12: 63976-63994 (2024) - [j37]Ta Viet Tai, Ma Pham Nhut Tan, Duong Hoang Tien, Nguyen Viet Ha, Trong-Thuc Hoang, Cong-Kha Pham, Tran Thi Thao Nguyen:
A Novel ECG Signal Quality Index Method Based on Skewness-MODWT Analysis. IEEE Access 12: 70184-70197 (2024) - [j36]Tuan-Kiet Dang, Khai-Duy Nguyen, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Cong-Kha Pham:
Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications. Future Internet 16(5): 157 (2024) - [j35]Binh Kieu-Do-Nguyen, Nguyen The Binh, Cuong Pham-Quoc, Huynh Phuc Nghi, Ngoc-Thinh Tran, Trong-Thuc Hoang, Cong-Kha Pham:
Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme. Inf. 15(7): 400 (2024) - [j34]Tuan-Kiet Dang, Khai-Duy Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3543-3547 (2024) - [j33]Thai-Ha Tran, Duc-Thuan Dam, Ba-Anh Dao, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang:
Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 573-586 (2024) - [c32]Binh Kieu-Do-Nguyen, Khai-Duy Nguyen, Tuan-Kiet Dang, Cong-Kha Pham, Trong-Thuc Hoang:
A Trusted Execution Environment RISC-V System on Chip. HCS 2024: 1 - [c31]Khai-Duy Nguyen, Tuan-Kiet Dang, Binh Kieu-Do-Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
RISC-V-Based System-on-Chips for IoT Applications. HCS 2024: 1 - [c30]Nhu-Hoang Nguyen, Tan-Phat Dang, Thanh-Dat Bui, Trong-Thuc Hoang, Cong-Kha Pham, Huu-Thuan Huynh:
Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding. ICCSA (Workshops 1) 2024: 110-121 - [c29]Phuc-Phan Duong, Trong-Thuc Hoang, Cong-Kha Pham:
A Strong 4 × 4 S-Box Using an Enhanced Tent Map. ISCAS 2024: 1-5 - [c28]Trong-Hung Nguyen, Nguyen The Binh, Huynh Phuc Nghi, Cong-Kha Pham, Trong-Thuc Hoang:
Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems. ISCAS 2024: 1-5 - [c27]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham:
A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. ISCAS 2024: 1-5 - [c26]Thai-Ha Tran, Van-Phuc Hoang, Duc-Hung Le, Trong-Thuc Hoang, Cong-Kha Pham:
An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode. ISCAS 2024: 1-5 - 2023
- [j32]Binh Kieu-Do-Nguyen, Cuong Pham-Quoc, Ngoc-Thinh Tran, Cong-Kha Pham, Trong-Thuc Hoang:
Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor. IEEE Access 11: 4879-4894 (2023) - [j31]Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment. Comput. Electr. Eng. 105: 108546 (2023) - [j30]Duc-Thuan Dam, Thai-Ha Tran, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang:
A Survey of Post-Quantum Cryptography: Start of a New Race. Cryptogr. 7(3): 40 (2023) - [j29]Trong-Hung Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography. Cryptogr. 7(4): 46 (2023) - [j28]Khai-Minh Ma, Duc-Hung Le, Cong-Kha Pham, Trong-Thuc Hoang:
Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA. Future Internet 15(5): 186 (2023) - [j27]Thai-Ha Tran, Ba-Anh Dao, Trong-Thuc Hoang, Van-Phuc Hoang, Cong-Kha Pham:
Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC. IEEE Trans. Computers 72(9): 2689-2700 (2023) - [c25]Thai-Ha Tran, Anh-Tien Le, Trong-Thuc Hoang, Van-Phuc Hoang, Cong-Kha Pham:
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks. ACM Great Lakes Symposium on VLSI 2023: 439-442 - [c24]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham:
In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. ISCAS 2023: 1-5 - [c23]Van-Phuc Hoang, Ngoc-Tuan Do, Trong-Thuc Hoang, Cong-Kha Pham:
Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks. MCSoC 2023: 9-14 - [c22]Nguyen The Binh, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Cong-Kha Pham, Cuong Pham-Quoc:
FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V. RIVF 2023: 31-36 - 2022
- [j26]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse. IEEE Access 10: 41852-41862 (2022) - [j25]Trong-Thuc Hoang, Ckristian Duran, Ronaldo Serrano, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling. IEEE Access 10: 46014-46027 (2022) - [j24]Binh Kieu-Do-Nguyen, Cuong Pham-Quoc, Ngoc-Thinh Tran, Cong-Kha Pham, Trong-Thuc Hoang:
Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA. Cryptogr. 6(2): 25 (2022) - [j23]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Cong-Kha Pham, Trong-Thuc Hoang:
ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. Cryptogr. 6(2): 30 (2022) - [j22]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham:
A Unified PUF and Crypto Core Exploiting the Metastability in Latches. Future Internet 14(10): 298 (2022) - [j21]Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Ronaldo Serrano, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham:
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2438-2442 (2022) - [c21]Tuan-Kiet Dang, Khai-Duy Nguyen, Quynh Nguyen Quang Nhu, Trong-Thuc Hoang, Cong-Kha Pham:
A System-on-Chip for IoT Applications with 16-bit Tiny Processor. ICICDT 2022: 44-47 - [c20]Binh Kieu-Do-Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Katsumi Inoue, Toshinori Usugi, Masanori Odaka, Shuichi Kameyama, Cong-Kha Pham:
High-speed FPGA-based Design and Implementation of Text Search Processor. ICICDT 2022: 109-112 - [c19]Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Spectre attack detection with Neutral Network on RISC-V processor. ISCAS 2022: 2467-2471 - [c18]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Trong-Thuc Hoang, Cong-Kha Pham:
A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. ISOCC 2022: 79-80 - [c17]Tuan-Kiet Dang, Ronaldo Serrano, Trong-Thuc Hoang, Cong-Kha Pham:
A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators. ISOCC 2022: 87-88 - [c16]Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
High-performance Multi-function HMAC-SHA2 FPGA Implementation. NEWCAS 2022: 30-34 - 2021
- [j20]Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks. IEEE Access 9: 24768-24786 (2021) - [j19]Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse. IEEE Access 9: 105748-105755 (2021) - [j18]Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure. IEEE Access 9: 151993-152014 (2021) - [j17]Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor. IEEE Access 9: 164597-164612 (2021) - [j16]Tuan-Kiet Dang, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Khai-Duy Nguyen, Xuan-Tu Tran, Cong-Kha Pham:
A proposal for enhancing training speed in deep learning models based on memory activity survey. IEICE Electron. Express 18(15): 20210252 (2021) - [j15]Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Xuan-Tu Tran, Cong-Kha Pham:
A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction. IEICE Electron. Express 18(16): 20210266 (2021) - [j14]Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Trong-Thuc Hoang, Ronaldo Serrano, Van-Phuc Hoang, Xuan-Tu Tran, Koichiro Ishibashi, Cong-Kha Pham:
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3182-3186 (2021) - [c15]Trong-Thuc Hoang, Ckristian Duran, Ronaldo Serrano, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture. HCS 2021: 1-16 - [c14]Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Cong-Kha Pham:
A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip. HCS 2021: 1-13 - [c13]Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. ISOCC 2021: 17-18 - [c12]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham:
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. ISOCC 2021: 375-376 - 2020
- [j13]Trong-Thuc Hoang, Ckristian Duran, Duc-Thinh Nguyen-Hoang, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Quick Boot of Trusted Execution Environment With Hardware Accelerators. IEEE Access 8: 74015-74023 (2020) - [j12]Trong-Thuc Hoang, Ckristian Duran, Khai-Duy Nguyen, Tuan-Kiet Dang, Quynh Nguyen Quang Nhu, Phuc Hong Than, Xuan-Tu Tran, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). IEICE Electron. Express 17(20): 20200282 (2020) - [j11]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS. Microprocess. Microsystems 73: 102970 (2020) - [c11]Trong-Thuc Hoang, Ckristian Duran, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j10]Duc-Hung Le, Trong-Thuc Hoang, Cong-Kha Pham:
A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC. IEICE Electron. Express 16(10): 20190116 (2019) - [j9]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB. Microprocess. Microsystems 69: 112-117 (2019) - [j8]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 472-476 (2019) - [j7]Trong-Thuc Hoang, Xuan-Thuan Nguyen, Duc-Hung Le, Cong-Kha Pham:
Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1723-1727 (2019) - [c10]Ngoc-Tu Bui, Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC. ICIT 2019: 835-840 - [c9]Takahiro Hosaka, Trong-Thuc Hoang, Van-Phuc Hoang, Duc-Hung Le, Katsumi Inoue, Cong-Kha Pham:
Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter. ISCAS 2019: 1 - [c8]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Katsumi Inoue, Ngoc-Tu Bui, Van-Phuc Hoang, Cong-Kha Pham:
A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS. ISCAS 2019: 1-4 - 2018
- [j6]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation. IEEE Access 6: 16046-16059 (2018) - [j5]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Trong-Thuc Hoang, Cong-Kha Pham:
A CORDIC-based QR decomposition for MIMO signal detector. IEICE Electron. Express 15(5) (2018) - [j4]Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC. IEICE Electron. Express 15(10): 20180302 (2018) - [j3]Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham:
Frequent items counter based on binary decoders. IEICE Electron. Express 15(20): 20180808 (2018) - [c7]Trong-Thuc Hoang, Cong-Kha Pham, Duc-Hung Le:
High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC. ISCAS 2018: 1-5 - [c6]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS. ISCAS 2018: 1-4 - [c5]Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations. MCSoC 2018: 225-232 - [c4]Katsumi Inoue, Trong-Thuc Hoang, Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study. PRIME 2018: 161-164 - [i3]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation. CoRR abs/1803.11207 (2018) - [i2]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An Efficient I/O Architecture for RAM-based Content-Addressable Memory on FPGA. CoRR abs/1804.02330 (2018) - [i1]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB. CoRR abs/1806.06902 (2018) - 2017
- [c3]Trong-Thuc Hoang, Xuan-Thuan Nguyen, Hong-Thu Nguyen, Nhu-Quynh Truong, Duc-Hung Le, Katsumi Inoue, Cong-Kha Pham:
FPGA-based frequent items counting using matrix of equality comparators. MWSCAS 2017: 285-288 - 2016
- [c2]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Trong-Thuc Hoang, Katsumi Inoue, Osamu Shimojo, Toshio Murayama, Kenji Tominaga, Cong-Kha Pham:
An efficient FPGA-based database processor for fast database analytics. ISCAS 2016: 1758-1761 - [c1]Trong-Thuc Hoang, Duc-Hung Le, Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham:
A hybrid adaptive CORDIC in 65nm SOTB CMOS process. ISCAS 2016: 2158-2161 - 2015
- [j2]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
Low-resource low-latency hybrid adaptive CORDIC with floating-point precision. IEICE Electron. Express 12(9): 20150258 (2015) - [j1]Trong-Thuc Hoang, Hong-Kiet Su, Hieu-Binh Nguyen, Duc-Hung Le, Huu-Thuan Huynh, Trong-Tu Bui, Cong-Kha Pham:
Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese. IEICE Electron. Express 12(14): 20150448 (2015)
Coauthor Index
[j39] [j38] [j37] [j36] [j35] [j34] [j33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [j32] [j31] [j30] [j29] [j28] [j27] [c25] [c24] [c23] [c22] [j26] [j25] [j24] [j23] [j22] [j21] [c21] [c20] [c19] [c18] [c17] [c16] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [c15] [c14] [c13] [c12] [j13] [j12] [j11] [c11] [j10] [j9] [j8] [j7] [c10] [c9] [c8] [j6] [j5] [j4] [j3] [c7] [c6] [c5] [c4] [i3] [i2] [i1] [c3] [c2] [c1] [j2] [j1]
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