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2020 – today
- 2023
[c5]Rachael J. Parker, Jyothi Bhaskarr Velamala, Kuan-Yueh James Shen, David Johnston
, Yao-Feng Chang, Stephen M. Ramey, Siang-jhih Sean Wu, Padma Penmatsa:
A Physical Unclonable Function Leveraging Hot Carrier Injection Aging. IRPS 2023: 1-5- 2022
- [c4]Jyothi Bhaskarr Velamala, Siang-jhih Sean Wu, Padma Penmatsa, Kuan-Yueh James Shen, David Johnston, Rachael J. Parker:
PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET Technology. CICC 2022: 1-2 - 2021
- [c3]Praveen Mosalikanti, Qi Wang, Kuan-Yueh James Shen, Mark Neidengard, Syed Feruz Syed Farooq, Vaughn Grossnickle, Nasser A. Kurd:
29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation. ISSCC 2021: 408-410
2010 – 2019
- 2019
- [c2]Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers, Kuan-Yueh James Shen, Andrey Mezhiba:
Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology. ISSCC 2019: 320-322 - 2018
- [j1]Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly:
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2109-2117 (2018) - 2016
- [c1]Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser A. Kurd:
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. ISSCC 2016: 330-331
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