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2020 – today
- 2024
[c16]Ruixuan Wang, Wengying Wen, Kyle Juretus, Xun Jiao:
PP-HDC: A Privacy-Preserving Inference Framework for Hyperdimensional Computing. DATE 2024: 1-6- [c15]Joseph Madera
, Kyle Juretus:
Boolean Domain Attack on Corrupt and Correct Based Logic Locking Techniques. ACM Great Lakes Symposium on VLSI 2024: 415-420 - [c14]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
DNA: DC Nodal Analysis Attack for Analog Circuits. ISCAS 2024: 1-5 - [c13]Syed A. Hamza, Moeness G. Amin, Kyle Juretus:
On the Roles of Sparse Array Configuration and Weights in Optimum Beamforming. WCNC 2024: 1-6 - 2023
- [j7]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
Hidden Costs of Analog Deobfuscation Attacks. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1802-1815 (2023) - [c12]Syed A. Hamza, Kyle Juretus, Moeness G. Amin, Fauzia Ahmad:
Deep Learning Sparse Array Design Using Binary Switching Configurations. ICASSP 2023: 1-5 - 2022
- [j6]Benjamin J. Lucas, Ali Alwan, Marion Murzello, Yazheng Tu, Pengzhou He, Andrew J. Schwartz, David Guevara, Ujjwal Guin, Kyle Juretus, Jiafeng Xie:
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator. IEEE Comput. Archit. Lett. 21(1): 17-20 (2022) - [c11]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
Practical Performance of Analog Attack Techniques. HOST 2022: 153-156 - 2021
- [j5]Kyle Juretus, Ioannis Savidis:
Synthesis of Hidden State Transitions for Sequential Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 11-23 (2021) - [j4]Kyle Juretus, Ioannis Savidis:
Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 38-51 (2021) - 2020
- [j3]Marko Jacovic, Kyle Juretus, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar:
Physical Layer Encryption for Wireless OFDM Communication Systems. J. Hardw. Syst. Secur. 4(3): 230-245 (2020) - [j2]Kyle Juretus, Ioannis Savidis:
Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1607-1620 (2020) - [c10]Kyle Juretus, Ioannis Savidis:
Reducing Logic Locking Key Leakage through the Scan Chain. ISCAS 2020: 1-5 - [c9]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
Security Vulnerabilities of Obfuscated Analog Circuits. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j1]James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar:
Securing Wireless Communication via Hardware-Based Packet Obfuscation. J. Hardw. Syst. Secur. 3(3): 261-272 (2019) - [c8]Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis:
Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. ACM Great Lakes Symposium on VLSI 2019: 483-488 - [c7]Kyle Juretus, Ioannis Savidis:
Increasing the SAT Attack Resiliency of In-Cone Logic Locking. ISCAS 2019: 1-5 - 2018
- [c6]Kyle Juretus, Ioannis Savidis:
Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security. APCCAS 2018: 366-369 - [c5]David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead:
Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. ICCD 2018: 83-91 - [c4]Kyle Juretus, Ioannis Savidis:
Time Domain Sequential Locking for Increased Security. ISCAS 2018: 1-5 - 2017
- [c3]James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar:
Physical gate based preamble obfuscation for securing wireless communication. ICNC 2017: 293-297 - 2016
- [c2]Kyle Juretus, Ioannis Savidis:
Reduced Overhead Gate Level Logic Encryption. ACM Great Lakes Symposium on VLSI 2016: 15-20 - [c1]Kyle Juretus, Ioannis Savidis:
Reducing logic encryption overhead through gate level key insertion. ISCAS 2016: 1714-1717
Coauthor Index
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