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2020 – today
- 2023
[c9]Yongding Tian
, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
Tydi-lang: A Language for Typed Streaming Hardware. SC Workshops 2023: 520-529- [c8]Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. VLDB Workshops 2023 - [i3]Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. CoRR abs/2308.13436 (2023) - 2022
- [i2]Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
Tydi-lang: A Language for Typed Streaming Hardware. CoRR abs/2212.06259 (2022) - 2021
- [j2]Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee:
Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow. J. Signal Process. Syst. 93(5): 565-586 (2021) - [c7]Johan Peltenburg, Ákos Hadnagy, Matthijs Brobbel, Robert Morrow, Zaid Al-Ars:
Tens of gigabytes per second JSON-to-Arrow conversion with FPGA accelerators. FPT 2021: 1-9 - [c6]Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars:
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. IJCAI 2021: 3470-3476 - [i1]Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars:
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. CoRR abs/2105.12151 (2021) - 2020
- [b1]Johan Peltenburg:
Methods for Efficient Integration of FPGA Accelerators with Big Data Systems. Delft University of Technology, Netherlands, 2020 - [j1]Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee:
Tydi: An Open Specification for Complex Data Structures Over Hardware Streams. IEEE Micro 40(4): 120-130 (2020) - [c5]Johan Peltenburg, Lars T. J. van Leeuwen, Joost Hoozemans, Jian Fang, Zaid Al-Ars, H. Peter Hofstee:
Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA. FPT 2020: 281-286
2010 – 2019
- 2019
- [c4]Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars:
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow. ARC 2019: 32-47 - [c3]Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee:
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow. FPL 2019: 270-277 - 2017
- [c2]Johan Peltenburg, Ahmad Hesam, Zaid Al-Ars:
Pushing Big Data into Accelerators: Can the JVM Saturate Our Hardware? ISC Workshops 2017: 220-236 - 2016
- [c1]Johan Peltenburg, Shanshan Ren, Zaid Al-Ars:
Maximizing systolic array efficiency to accelerate the PairHMM Forward Algorithm. BIBM 2016: 758-762
Coauthor Index
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