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2020 – today
- 2024
[j6]Tae-Hyun Kim
, Juhyun Park, In-Jun Jung, Hoonki Kim, Taejoong Song, Seong-Ook Jung:
A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. IEEE Trans. Circuits Syst. II Express Briefs 71(10): 4531-4535 (2024)- 2023
- [c6]Seungyoung Lee, Sungyup Jung, Yunkyeong Jang, Jungho Do, Jisu Yu, Hyeoungyu You, Minjae Jeong, Jinyoung Lim, Jiyun Han, Sangdo Park, Yongdeok Kim, Jooyeon Kwon, Hoonki Kim, Seiseung Yoon:
Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j5]Taejoong Song, Hoonki Kim, Woojin Rim, Hakchul Jung, Changnam Park, Inhak Lee, Sanghoon Baek, Jonghoon Jung:
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. IEEE J. Solid State Circuits 57(1): 236-244 (2022) - [c5]Taejoong Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, Woojin Rim, Sanghoon Baek, Sangyeop Baeck, Jonghoon Jung:
3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. CICC 2022: 1-7 - 2021
- [j4]Hanwool Jeong, Tae Hyun Kim, Changnam Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung:
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. IEEE J. Solid State Circuits 56(2): 554-565 (2021) - [c4]Taejoong Song, Woojin Rim, Hoonki Kim, Keun Hwi Cho, Taeyeong Kim, Taejung Lee, Geumjong Bae, Dong-Won Kim, S. D. Kwon, Sanghoon Baek, Jonghoon Jung, Jongwook Kye, Hakchul Jung, Hyungtae Kim, Soon-Moon Jung, Jaehong Park:
24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. ISSCC 2021: 338-340 - 2020
- [j3]Tae Hyun Kim, Hanwool Jeong, Juhyun Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung:
An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. IEEE Access 8: 187126-187139 (2020)
2010 – 2019
- 2019
- [j2]Hanwool Jeong, Se Hyeok Oh, Tae Woo Oh, Hoonki Kim, Changnam Park, Woojin Rim, Taejoong Song, Seong-Ook Jung:
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving. IEEE J. Solid State Circuits 54(3): 896-906 (2019) - 2018
- [c3]Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi, Jong Shik Yoon:
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. ISSCC 2018: 198-200 - [c2]Woong Choi, Jongsun Park, Hoonki Kim, Changnam Park, Taejoong Song:
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. VLSI Circuits 2018: 17-18 - 2017
- [j1]Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Giyong Yang, Hoonki Kim, Sanghoon Baek, Jonghoon Jung, Bongjae Kwon, Sungwee Cho, Hyuntaek Jung, Yongjae Choo, Jaeseung Choi:
A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. IEEE J. Solid State Circuits 52(1): 240-249 (2017) - [c1]Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi:
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. ISSCC 2017: 208-209
Coauthor Index
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