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2020 – today
- 2023
[j3]Leandro Passetti
, Damián A. Morero, Benjamín T. Reyes, Mario R. Hueda:
Adaptive Digital Compensation of Analog Impairments in Frequency Interleaved ADC for Next-Generation High-Speed Communication Receivers. IEEE Access 11: 124855-124868 (2023)- [c4]Leandro Passetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda:
Evaluation of the Performance Impact of Clock Jitter and Phase Noise in a Two-Band Frequency-Interleaved ADC. ICECS 2023: 1-4 - 2021
- [j2]Fredy Solis, Álvaro Fernandez Bocco, Agustin C. Galetto, Leandro Passetti, Mario R. Hueda, Benjamín T. Reyes:
A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS. Int. J. Circuit Theory Appl. 49(10): 3171-3185 (2021) - [c3]Leandro Passetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda:
Reduced Complexity Backpropagation-Based Adaptive Compensation of Frequency Interleaved ADC for Digital Communication Receivers. ISCAS 2021: 1-5 - 2020
- [c2]Leandro Passetti, Agustin C. Galetto, Diego J. Hernando, Damián A. Morero, Benjamín T. Reyes, Mario R. Hueda:
Backpropagation-Based Background Compensation of Frequency Interleaved ADC for Coherent Optical Receivers. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j1]Benjamín T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti, Fredy Solis, Mario R. Hueda:
An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2064-2076 (2019) - 2018
- [c1]Benjamín T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti, Fredy Solis, Mario R. Hueda:
An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing. LASCAS 2018: 1-4
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