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ORCIDLakshmi P. Rao
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2020 – today
- 2024
[j5]Bo Zhang
, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao, Afshin Momtaz:
A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology. IEEE J. Solid State Circuits 59(1): 8-18 (2024)- [c4]Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo-Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao:
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. ISSCC 2024: 338-340 - 2023
- [c3]Bo Zhang, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao, Afshin Momtaz:
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology. ISSCC 2023: 108-109
2010 – 2019
- 2016
- [j4]Namik Kocaman, Tamer A. Ali, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz:
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS. IEEE J. Solid State Circuits 51(4): 881-892 (2016) - [c2]Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman:
A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [c1]Tamer A. Ali, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz, Namik Kocaman:
A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS. VLSIC 2015: 348- - 2012
- [j3]Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst:
Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 188-192 (2012) - [j2]Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst:
Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(3): 652-663 (2012) - [j1]Lakshmi P. Rao, Nattapol Sitthimahachaikul, Paul J. Hurst:
Correcting the Effects of Mismatches in Time-Interleaved Analog Adaptive FIR Equalizers. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2529-2542 (2012)
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last updated on 2024-10-07 21:19 CEST by the dblp team
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