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2020 – today
- 2024
[c11]Yusuke Shuto, Jun Okuno, Tsubasa Yonai, Ryo Ono, Peter Reinig, Maximilian Lederer, Konrad Seidel, Ruben Alcala, Thomas Mikolajick, Uwe Schroeder, Taku Umebayashi, Kentaro Akiyama:
HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85°C. VLSI Technology and Circuits 2024: 1-2- 2021
- [c10]Jun Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shuto, Fumitaka Sugaya, Monica Materano, Tarek Ali, Maximilian Lederer
, Kati Kühnel, Konrad Seidel, Uwe Schroeder, Thomas Mikolajick, Masanori Tsukamoto, Taku Umebayashi:
High-Endurance and Low-Voltage operation of 1T1C FeRAM Arrays for Nonvolatile Memory Application. IMW 2021: 1-3 - [c9]Daisuke Saito, Toshiyuki Kobayashi, Hiroki Koga, Nicolo Ronchi, Kaustuv Banerjee, Yusuke Shuto, Jun Okuno, Kenta Konishi, Luca Di Piazza, Arindam Mallik, Jan Van Houdt, Masanori Tsukamoto, Kazunobu Ohkuri, Taku Umebayashi, Takayuki Ezaki:
Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications. VLSI Circuits 2021: 1-2
2010 – 2019
- 2018
- [c8]Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. NVMSA 2018: 91-98 - [c7]Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. ReConFig 2018: 1-6 - 2016
- [c6]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Energy performance of nonvolatile power-gating SRAM using SOTB technology. ESSCIRC 2016: 95-98 - [c5]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Design and implementation of nonvolatile power-gating SRAM using SOTB technology. ISLPED 2016: 338-343 - 2015
- [c4]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology. DATE 2015: 866-871 - 2014
- [c3]Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology. APCCAS 2014: 699-702 - 2013
- [c2]Ryosho Nakane, Yusuke Shuto, Hiroaki Sukegawa, Zhenchao Wen, Shuu'ichirou Yamamoto, Seiji Mitani, Masaaki Tanaka, Koichiro Inomata, Satoshi Sugahara:
Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service. ESSDERC 2013: 272-275
2000 – 2009
- 2009
- [c1]Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara:
Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices. CICC 2009: 531-534
Coauthor Index
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