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2020 – today
- 2024
[b1]Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman:
Structural Decision Diagrams in Digital Test - Theory and Applications. Springer 2024, ISBN 978-3-031-44733-4, pp. 1-572- [j18]Mohammad Hasan Ahmadilivani
, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. ACM Comput. Surv. 56(6): 141:1-141:39 (2024) - [c95]Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio:
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. DDECS 2024: 19-24 - [c94]Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin:
AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. ETS 2024: 1-4 - [c93]Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. IOLTS 2024: 1-7 - [c92]Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik:
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. ISQED 2024: 1-8 - [c91]Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab:
Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS 2024: 1-2 - [c90]Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola:
Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS 2024: 1-11 - [i30]Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik:
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. CoRR abs/2401.09509 (2024) - [i29]Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin:
AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. CoRR abs/2403.02936 (2024) - [i28]Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio:
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. CoRR abs/2403.02946 (2024) - [i27]Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. CoRR abs/2405.10658 (2024) - [i26]Seyedhamidreza Mousavi, Mohammad Hasan Ahmadilivani, Jaan Raik, Maksim Jenihhin, Masoud Daneshtalab:
ProAct: Progressive Training for Hybrid Clipped Activation Function to Enhance Resilience of DNNs. CoRR abs/2406.06313 (2024) - 2023
- [j17]Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin:
Applying RIS-Based Communication for Collaborative Computing in a Swarm of Drones. IEEE Access 11: 70093-70109 (2023) - [j16]Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri:
An automated method for mining high-quality assertion sets. Microprocess. Microsystems 97: 104773 (2023) - [c89]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. AICAS 2023: 1-5 - [c88]Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik:
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. DDECS 2023: 124-127 - [c87]Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov:
On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT 2023: 1-6 - [c86]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment. ETS 2023: 1-6 - [c85]Hardi Selg, Maksim Jenihhin, Peeter Ellervee, Jaan Raik:
ML-Based Online Design Error Localization for RISC-V Implementations. IOLTS 2023: 1-7 - [c84]Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper:
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. ISQED 2023: 1-8 - [c83]Foisal Ahmed, Maksim Jenihhin:
Holistic IJTAG-based External and Internal Fault Monitoring in UAVs. LATS 2023: 1-6 - [c82]Xinhui Lai, Maksim Jenihhin:
Analyzing Side-Channel Attack Vulnerabilities at RTL. LATS 2023: 1-2 - [c81]Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri:
Special Session: Approximation and Fault Resiliency of DNN Accelerators. VTS 2023: 1-10 - [e3]Maksim Jenihhin, Hana Kubátová, Nele Metens, Jaan Raik, Foisal Ahmed, Jan Belohoubek:
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023. IEEE 2023, ISBN 979-8-3503-3277-3 [contents] - [i25]Tanvir Ahmad Tarique, Foisal Ahmed, Maksim Jenihhin, Liakot Ali:
Unsupervised Recycled FPGA Detection Using Symmetry Analysis. CoRR abs/2303.01807 (2023) - [i24]Foisal Ahmed, Maksim Jenihhin:
Holistic IJTAG-based External and Internal Fault Monitoring in UAVs. CoRR abs/2303.01816 (2023) - [i23]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessment. CoRR abs/2303.06931 (2023) - [i22]Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper:
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. CoRR abs/2303.08226 (2023) - [i21]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. CoRR abs/2305.05750 (2023) - [i20]Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik:
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. CoRR abs/2305.19733 (2023) - [i19]Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani, Maksim Jenihhin:
A Novel Fault-Tolerant Logic Style with Self-Checking Capability. CoRR abs/2306.00844 (2023) - [i18]Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri:
Special Session: Approximation and Fault Resiliency of DNN Accelerators. CoRR abs/2306.04645 (2023) - [i17]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. CoRR abs/2306.09973 (2023) - [i16]Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov:
On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR abs/2308.15917 (2023) - 2022
- [j15]Foisal Ahmed, Maksim Jenihhin:
A Survey on UAV Computing Platforms: A Hardware Reliability Perspective. Sensors 22(16): 6286 (2022) - [c80]Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi:
MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. IOLTS 2022: 1-5 - [c79]Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani, Maksim Jenihhin:
A Novel Fault-Tolerant Logic Style with Self-Checking Capability. IOLTS 2022: 1-6 - [c78]Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI 2022: 32-37 - [c77]Cemil Cem Gürsoy, Daniel Kraak, Foisal Ahmed, Mottaqiallah Taouil, Maksim Jenihhin, Said Hamdioui:
On BTI Aging Rejuvenation in Memory Address Decoders. LATS 2022: 1-6 - [i15]Cemil Cem Gürsoy, Daniel Kraak, Foisal Ahmed, Mottaqiallah Taouil, Maksim Jenihhin, Said Hamdioui:
On BTI Aging Rejuvenation in Memory Address Decoders. CoRR abs/2212.09356 (2022) - 2021
- [j14]Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin:
Fast and Fair Computation Offloading Management in a Swarm of Drones Using a Rating-Based Federated Learning Approach. IEEE Access 9: 113832-113849 (2021) - [c76]Aneesh Balakrishnan, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu:
Modeling Soft-Error Reliability Under Variability. DFT 2021: 1-6 - [c75]Hardi Selg, Maksim Jenihhin, Peeter Ellervee:
JÄNES: A NAS Framework for ML-based EDA Applications. DFT 2021: 1-6 - [c74]Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar:
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD 2021: 557-561 - [c73]Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux:
Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis. ISQED 2021: 24-30 - [c72]Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin:
Edge-to-Fog Collaborative Computing in a Swarm of Drones. MEDI Workshops 2021: 78-87 - [c71]Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri:
A Methodology for Automated Mining of Compact and Accurate Assertion Sets. NorCAS 2021: 1-7 - [c70]Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin:
On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. VLSI-SoC 2021: 1-6 - [i14]Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer:
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. CoRR abs/2103.05106 (2021) - [i13]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. CoRR abs/2104.01812 (2021) - [i12]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. CoRR abs/2104.01900 (2021) - [i11]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. CoRR abs/2104.01908 (2021) - 2020
- [j13]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. 36(1): 87-103 (2020) - [j12]Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems 77: 103117 (2020) - [c69]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE 2020: 388-393 - [c68]Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil, Said Hamdioui:
A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs. DATE 2020: 792-797 - [c67]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD 2020: 646-650 - [c66]Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer:
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. IOLTS 2020: 1-6 - [c65]Hardi Selg, Maksim Jenihhin, Peeter Ellervee:
Wafer-Level Die Re-Test Success Prediction Using Machine Learning. LATS 2020: 1-5 - [c64]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. MECO 2020: 1-5 - [c63]Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul:
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. VLSI-SOC 2020: 16-21 - [c62]Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sánchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer:
Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks. VTS 2020: 1-9 - [i10]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. CoRR abs/2001.09982 (2020) - [i9]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Efficient Fault Injection based on Dynamic HDL Slicing Technique. CoRR abs/2002.00787 (2020) - [i8]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. CoRR abs/2002.11108 (2020) - [i7]Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul:
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. CoRR abs/2008.08409 (2020) - [i6]Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. CoRR abs/2009.11621 (2020)
2010 – 2019
- 2019
- [j11]Syed Rameez Naqvi, Anjum Zahid, Lina Sawalha, Syed Saud Naqvi, Tallha Akram, Sajjad Ali Haider, Kumar Yelamarthi, Maksim Jenihhin:
An optimization framework for dynamic pipeline management in computing systems. Comput. Electr. Eng. 78: 242-258 (2019) - [j10]Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu:
Understanding multidimensional verification: Where functional meets non-functional. Microprocess. Microsystems 71 (2019) - [c61]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. AHS 2019: 72-78 - [c60]Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. DDECS 2019: 1-4 - [c59]Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu:
Challenges of Reliability Assessment and Enhancement in Autonomous Systems. DFT 2019: 1-6 - [c58]Raimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin:
True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. DSD 2019: 492-499 - [c57]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS 2019: 1-6 - [c56]Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi:
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS 2019: 1-6 - [c55]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Efficient Fault Injection based on Dynamic HDL Slicing Technique. IOLTS 2019: 52-53 - [c54]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. IOLTS 2019: 239-242 - [c53]Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran:
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS 2019: 299-304 - [c52]Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui:
Software-Based Mitigation for Memory Address Decoder Aging. LATS 2019: 1-6 - [c51]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. LATS 2019: 1-6 - [c50]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. NORCAS 2019: 1-7 - [c49]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. NORCAS 2019: 1-7 - [c48]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) 2019: 21-44 - [c47]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC 2019: 82-87 - [c46]Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin:
On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks. VLSI-SoC 2019: 335-340 - [i5]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. CoRR abs/1907.12325 (2019) - [i4]Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik:
Towards Multidimensional Verification: Where Functional Meets Non-Functional. CoRR abs/1908.00314 (2019) - [i3]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR abs/1908.02986 (2019) - [i2]Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu:
Challenges of Reliability Assessment and Enhancement in Autonomous Systems. CoRR abs/1909.03040 (2019) - [i1]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR abs/1912.01561 (2019) - 2018
- [j9]Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi:
Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. 81: 252-261 (2018) - [c45]Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin:
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. DDECS 2018: 67-72 - [c44]Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey:
Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS 2018: 147-152 - [c43]Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda:
RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. EWME 2018: 45-50 - [c42]Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies:
Timing-critical path analysis with structurally synthesized BDDs. MECO 2018: 1-6 - [c41]Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik:
Towards Multidimensional Verification: Where Functional Meets Non-Functional. NORCAS 2018: 1-7 - [c40]Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin:
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS 2018: 1-6 - [c39]Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin:
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. VLSI-SoC 2018: 207-212 - [e2]Jari Nurmi, Peeter Ellervee, Juri Mihhailov, Maksim Jenihhin, Kalle Tammemäe:
2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, October 30-31, 2018. IEEE 2018, ISBN 978-1-5386-7656-1 [contents] - 2017
- [c38]Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke:
BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE 2017: 115-120 - [c37]Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik:
A scalable technique to identify true critical paths in sequential circuits. DDECS 2017: 152-157 - [c36]Jüri Vain, Leonidas Tsiopoulos, Vyacheslav S. Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik:
Multi-Fragment Markov Model Guided Online Test Generation for MPSoC. ICTERI 2017: 594-607 - 2016
- [j8]Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros:
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. 32(3): 273-289 (2016) - [c35]Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar:
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS 2016: 304-309 - [c34]Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi Kohan:
Universal mitigation of NBTI-induced aging by design randomization. EWDTS 2016: 1-5 - [c33]Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao:
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL 2016: 1-8 - [c32]Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
Gate-level modelling of NBTI-induced delays under process variations. LATS 2016: 75-80 - 2015
- [c31]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik:
SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. DDECS 2015: 71-74 - [c30]Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls:
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS 2015: 223-228 - [c29]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik:
FSMD RTL design manipulation for clock interface abstraction. ICACCI 2015: 463-468 - [c28]N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls:
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS 2015: 1-6 - 2014
- [j7]Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke:
Automated Design Error Localization in RTL Designs. IEEE Des. Test 31(1): 83-92 (2014) - [c27]Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar:
Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications 2014: 425-436 - [c26]Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti:
Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW 2014: 1-6 - 2013
- [j6]Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin:
Automated design error debug using high-level decision diagrams and mutation operators. Microprocess. Microsystems 37(4-5): 505-513 (2013) - [c25]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik:
Extensible open-source framework for translating RTL VHDL IP cores to SystemC. DDECS 2013: 112-115 - [c24]Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls:
Identifying NBTI-Critical Paths in Nanoscale Logic. DSD 2013: 136-141 - [c23]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu:
Performance analysis of cosimulating processor core in VHDL and SystemC. ICACCI 2013: 563-568 - [c22]Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
Assessment of diagnostic test for automated bug localization. LATW 2013: 1-6 - 2012
- [j5]Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
On the Reuse of TLM Mutation Analysis at RTL. J. Electron. Test. 28(4): 435-448 (2012) - [j4]Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara:
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. 28(4): 511-521 (2012) - [c21]Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi:
Combining dynamic slicing and mutation operators for ESL correction. ETS 2012: 1-6 - [c20]Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. LATW 2012: 1-6 - [c19]Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov:
PSL assertion checkers synthesis with ASM based HLS tool ABELITE. LATW 2012: 1-6 - [c18]Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke:
Localization of Bugs in Processor Designs Using zamiaCAD Framework. MTV 2012: 41-47 - [c17]Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov:
A scalable model based RTL framework zamiaCAD for static analysis. VLSI-SoC 2012: 171-176 - [e1]Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin:
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8 [contents] - 2011
- [c16]Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara:
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS 2011: 147-152 - [c15]Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov:
Automated test bench generation for high-level synthesis flow ABELITE. EWDTS 2011: 13-16 - [c14]Maksim Jenihhin, Maksim Gorev, Vadim Pesonen, Dmitri Mihhailov, Peeter Ellervee, Hiie Hinrikus, Maie Bachmann, Jaanus Lass:
EEG Analyzer prototype based on FPGA. ISPA 2011: 101-106 - [c13]Valerio Guarnieri, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
Mutation analysis for SystemC designs at TLM. LATW 2011: 1-6 - 2010
- [c12]Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko:
Constraint-based test pattern generation at the Register-Transfer Level. DDECS 2010: 352-357 - [c11]Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova:
An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS 2010: 13-16 - [c10]Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe Di Guglielmo, Franco Fummi:
Mutation analysis with high-level decision diagrams. LATW 2010: 1-6
2000 – 2009
- 2009
- [j3]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar:
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electron. Test. 25(6): 289-300 (2009) - [c9]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar:
High-Level Decision Diagrams based coverage metrics for verification and test. LATW 2009: 1-6 - 2008
- [j2]Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin:
Mixed hierarchical-functional fault models for targeting sequential cores. J. Syst. Archit. 54(3-4): 465-477 (2008) - [c8]Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee:
Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206 - [c7]Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee:
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227 - [c6]Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz:
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD 2008: 729-734 - [c5]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar:
Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. ETS 2008: 61-68 - 2007
- [c4]Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski:
Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40 - 2006
- [j1]Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin:
Test Time Minimization for Hybrid BIST of Core-Based Systems. J. Comput. Sci. Technol. 21(6): 907-912 (2006) - 2004
- [c3]Raimund Ubar, Maksim Jenihhin:
Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. DELTA 2004: 3-8 - 2003
- [c2]Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin:
Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003: 318-325 - [c1]Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin:
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. DFT 2003: 225-
Coauthor Index
Letícia Maria Veiras Bolzani
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
Stephen Adeboye Oyeniran
aka: Adeboye Stephen Oyeniran
aka: Adeboye Stephen Oyeniran
[b1] [j18] [c95] [c94] [c93] [c92] [c91] [c90] [i30] [i29] [i28] [i27] [i26] [j16] [c89] [c88] [c86] [c85] [c84] [c81] [e3] [i23] [i22] [i21] [i20] [i18] [i17] [c78] [c74] [c71] [j13] [j12] [c69] [c67] [i10] [i9] [i8] [i6] [j10] [c60] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c48] [c47] [i5] [i4] [i3] [i1] [j9] [c45] [c44] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [j8] [c35] [c33] [c32] [c31] [c30] [c29] [c28] [j7] [c27] [c26] [j6] [c25] [c24] [c23] [c22] [j5] [j4] [c21] [c20] [c19] [c18] [c17] [e1] [c16] [c15] [c13] [c12] [c11] [c10] [j3] [c9] [j2] [c8] [c7] [c6] [c5] [c4]
[b1] [c78] [c74] [i14] [j13] [j12] [c67] [c66] [i6] [c60] [c58] [c57] [c53] [c51] [c48] [c47] [i5] [i3] [j9] [c42] [c40] [c37] [j8] [c35] [c32] [c30] [j7] [c27] [c26] [j6] [c24] [c22] [j5] [j4] [c21] [c20] [e1] [c16] [c15] [c13] [c12] [c11] [c10] [j3] [c9] [j2] [c8] [c7] [c6] [c5] [c4] [j1] [c3] [c2] [c1]
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