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ORCIDHusain Parvez
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2020 – today
- 2021
[j8]Muhammad Mazher Iqbal
, Husain Parvez, Fasahat Hussain, Muhammad Rashid:
An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells. J. Circuits Syst. Comput. 30(4): 2150065:1-2150065:24 (2021)
2010 – 2019
- 2017
- [j7]Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid:
Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing. Int. J. Reconfigurable Comput. 2017: 7021056:1-7021056:9 (2017) - [c14]Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid:
Logic algebra for exploiting shared SRAM-table based FPGAs for large LUT inputs. INTELLECT 2017: 1-4 - [c13]Muhammad Mazher Iqbal, Husain Parvez:
Optimizing routing network of shared hardware design for multiple application circuits. INTELLECT 2017: 1-4 - 2016
- [j6]Muhammad Mazher Iqbal, Husain Parvez, Muhammad Rashid:
"Multi-Circuit": Automatic Generation of an Application Specific Configurable Core for Known Set of Application Circuits. J. Circuits Syst. Comput. 25(9): 1650102:1-1650102:17 (2016) - [c12]Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid:
Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs. FPT 2016: 229-232 - 2015
- [j5]Ali Asghar, Husain Parvez:
An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs. Int. J. Reconfigurable Comput. 2015: 756014:1-756014:10 (2015) - 2014
- [c11]Ali Asghar, Husain Parvez:
Diffusion-Based Placement Algorithm for Reducing High Interconnect Demand in Congested Regions of FPGAs. ARC 2014: 291-297 - [c10]Muhammad Amin Qureshi, Husain Parvez:
Design-space exploration between FPGA and ASIF. ReCoSoC 2014: 1-5 - [c9]Baqar Raza, Husain Parvez, Muhammad Mohiuddin:
Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm. ReCoSoC 2014: 1-5 - 2013
- [j4]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. Microelectron. J. 44(12): 1052-1062 (2013) - 2012
- [j3]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess. Microsystems 36(8): 588-605 (2012) - 2011
- [j2]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfigurable Comput. 2011: 121404:1-121404:18 (2011) - [j1]Husain Parvez, Zied Marrakchi, Alp Kiliç, Habib Mehrez:
Application-Specific FPGA using heterogeneous logic blocks. ACM Trans. Reconfigurable Technol. Syst. 4(3): 24:1-24:14 (2011) - [c8]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC 2011: 218-229 - 2010
- [c7]Zied Marrakchi, Husain Parvez, Alp Kiliç, Habib Mehrez, Hmaied Marrakchi:
On the optimization of FPGA area depending on target applications. APCCAS 2010: 308-311 - [c6]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Application Specific FPGA Using Heterogeneous Logic Blocks. ARC 2010: 92-109 - [c5]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA 2010: 290 - [c4]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Exploration of Heterogeneous FPGA Architectures. ReCoSoC 2010: 37-44
2000 – 2009
- 2009
- [c3]Husain Parvez, Zied Marrakchi, Habib Mehrez:
ASIF: Application Specific Inflexible FPGA. FPT 2009: 112-119 - 2008
- [c2]Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez:
A new coarse-grained FPGA architecture exploration environment. FPT 2008: 285-288 - [c1]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig 2008: 121-126
Coauthor Index
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