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ORCIDMasakazu Hioki
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2020 – today
- 2024
[j7]Hiroshi Fuketa
, Toshihiro Katashita, Yohei Hori, Masakazu Hioki:
Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. IEEE Access 12: 102470-102480 (2024)- 2022
- [j6]Ippei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki:
An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer. IEEE J. Solid State Circuits 57(12): 3704-3715 (2022) - [c8]Ippei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki:
A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement. ISSCC 2022: 1-3
2010 – 2019
- 2018
- [j5]Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike:
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. IEICE Trans. Inf. Syst. 101-D(2): 303-313 (2018) - 2016
- [j4]Masakazu Hioki, Hanpei Koike:
Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology. IEICE Trans. Inf. Syst. 99-D(12): 3082-3089 (2016) - 2013
- [c7]Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi:
Fully-functional FPGA prototype with fine-grain programmable body biasing. FPGA 2013: 73-80
2000 – 2009
- 2008
- [j3]Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa:
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. ACM Trans. Reconfigurable Technol. Syst. 1(1): 3:1-3:31 (2008) - 2007
- [j2]Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. IEICE Trans. Inf. Syst. 90-D(12): 1947-1955 (2007) - [c6]Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. FPGA 2007: 169-177 - [c5]Masakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi:
A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. FPT 2007: 285-288 - 2006
- [c4]Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA 2006: 223 - [c3]Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Evaluation of granularity on threshold voltage control in flex power FPGA. FPT 2006: 17-24 - [c2]Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Optimal set of body bias voltages for an FPGA with field-programmable Vth components. FPT 2006: 329-332 - 2004
- [j1]Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. IEICE Trans. Inf. Syst. 87-D(8): 2004-2010 (2004) - [c1]Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA 2004: 257
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