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2020 – today
- 2024
[c5]Lilia Zaourar
, Mohamed Benazouz, Ayoub Mouhagir, Carlos Falquez, Antoni Portero, Nam Ho, Estela Suarez, Polydoros Petrakis, Manolis Marazakis, Francesco Sgherzi, Ivan Fernandez, Romain Dolbeau, Dirk Pleiter:
Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC. ARCS 2024: 251-265- 2023
- [c4]Antoni Portero, Carlos Falquez, Nam Ho, Polydoros Petrakis, Stepan Nassyr, Manolis Marazakis, Romain Dolbeau, Jorge Alejandro Nocua Cifuentes, Luis Bertran Alvarez, Dirk Pleiter, Estela Suarez:
COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores. ARCS 2023: 105-119 - 2022
- [j3]Romain Dolbeau:
Correction to: Theoretical peak FLOPS per instruction set: a tutorial. J. Supercomput. 78(10): 12929 (2022) - 2021
- [c3]Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau:
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS 2021: 18-29
2010 – 2019
- 2018
- [j2]Romain Dolbeau:
Theoretical peak FLOPS per instruction set: a tutorial. J. Supercomput. 74(3): 1341-1377 (2018) - 2016
- [c2]Issam Said, Pierre Fortin, Jean Luc Lamotte, Romain Dolbeau, Henri Calandra:
On the efficiency of the accelerated processing unit for scientific computing. SpringSim (HPS) 2016: 25 - 2014
- [i1]Denis Barthou, Olivier Brand-Foissac, Romain Dolbeau, Gilbert Grosdidier, Christine Eisenbeis, Michael Kruse, Olivier Pène, Konstantin Petrov, Claude Tadonki:
Automated Code Generation for Lattice Quantum Chromodynamics and beyond. CoRR abs/1401.2039 (2014) - 2013
- [c1]Henri Calandra, Romain Dolbeau, Pierre Fortin, Jean Luc Lamotte, Issam Said:
Evaluation of Successive CPUs/APUs/GPUs Based on an OpenCL Finite Difference Stencil. PDP 2013: 405-409
2000 – 2009
- 2004
- [j1]Romain Dolbeau, André Seznec:
CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors. J. Instr. Level Parallelism 6 (2004)
Coauthor Index
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