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2020 – today
- 2021
[c8]Markus Probeck, Inés Ruíz, Gernot Ramminger, Christoff Fourie, Pirmin Maier, Martin Ickerott, Cornelia Storch, Anna Homolka, Sybrand Jacobus Muller, Himanshu Tiwari, André Stumpf, Sooyeon Chun, Cristina Mattos, Amelie Lindmayer, Fahad Jahangir, Pilar Endara, Fabian Berndt, Mario Dohr, Wolfgang Kapferer, Christian Schleicher, Stefan Ralser, Florian Innerbichler, Michael Riffler, Martin Siklar, Dora Aifantopoulou, Sideris Paralykidis, Camille Pinet
, Gabriel Jaffrain, Annalaura di Federico, Marco Corsi, Tobias Langanke, Hans Dufourmont:
CLC+ Backbone: Set the Scene in Copernicus for the Coming Decade. IGARSS 2021: 2076-2079- [c7]Seyfi S. Bazarjani, Jongwoo Lee, Marco Corsi:
Session 10 Overview: Continuous-Time ADCs and DACs Data Converter Subcommittee. ISSCC 2021: 162-163 - [c6]Youngcheol Chae, Yun-Shiang Shu, Jens Anders, Viola Schaffer, Takashi Oshima, Marco Corsi:
F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits. ISSCC 2021: 517-519
2010 – 2019
- 2018
- [i2]Barbara Pernici, Chiara Francalanci, Gabriele Scalia, Marco Corsi, Domenico Grandoni, Mariano Alfonso Biscardi:
Geolocating social media posts for emergency mapping. CoRR abs/1801.06861 (2018) - 2013
- [i1]Yaacov Weingarten, Stewart Bryant, Daniele Ceccarelli, Diego Caviglia, Francesco Fondelli, Marco Corsi, Bo Wu, Xuehui Dai:
Applicability of MPLS Transport Profile for Ring Topologies. RFC 6974: 1-30 (2013) - 2012
- [c5]Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi:
A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. ISSCC 2012: 158-160 - [c4]Vijay Rentala, Venkatesh Srinivasan, Victoria Wang, Srinath Ramaswamy, Baher Haroun, Marco Corsi:
Low power ADC's for wireless communications. MWSCAS 2012: 694-697 - 2011
- [c3]Robert Payne, Charles K. Sestok, William Bright, Manar El-Chammas, Marco Corsi, David Smith, Noam Tal:
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. ISSCC 2011: 182-184 - 2010
- [j3]Robert Payne, Marco Corsi, David Smith, Tien-Ling Hsieh, Scott Kaylor:
A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. IEEE J. Solid State Circuits 45(12): 2613-2622 (2010) - [j2]Kailash Chandrashekar, Marco Corsi, John W. Fattaruso, Bertan Bakkaloglu:
A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling. IEEE Trans. Circuits Syst. II Express Briefs 57-II(8): 602-606 (2010) - [c2]Robert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh:
A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. ISSCC 2010: 294-295
2000 – 2009
- 2003
- [j1]Kenneth Maclean, Marco Corsi, Richard K. Hester, James Quarfoot, Peter Melsa, Robert L. Halbach, Carmen Kozak, Tobin Hagan:
A 610-mW zero-overhead class-G full-rate ADSL CO line driver. IEEE J. Solid State Circuits 38(12): 2191-2200 (2003) - [c1]James R. Hellums, Richard K. Hester, Marco Corsi, Tobin Hagan, Robert L. Halbach:
An ADSL integrated active hybrid circuit. ESSCIRC 2003: 517-520
Coauthor Index
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