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2020 – today
- 2024
[j15]Hongyang Pan
, Yinshui Xia, Lunyao Wang, Zhufei Chu:
Semi-Tensor Product-Based Exact Synthesis for Logic Rewriting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1093-1106 (2024)- [c10]Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, Fan Yang, Xuan Zeng, Zhufei Chu:
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping. DATE 2024: 1-6 - 2023
- [i1]Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, Fan Yang, Xuan Zeng, Zhufei Chu:
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping. CoRR abs/2312.00421 (2023) - 2022
- [j14]Qing Wan, Changjin Wan, Huaqiang Wu, Yuchao Yang, Xiaohe Huang, Peng Zhou, Lin Chen, Tian-Yu Wang, Yi Li, Kanhao Xue, Yu-Hui He, Xiangshui Miao, Xi Li, Chenchen Xie, Houpeng Chen, Zhitang Song, Hong Wang, Yue Hao, Junyao Zhang, Jia Huang, Zheng Yu Ren, Li Qiang Zhu, Jianyu Du, Chen Ge, Yang Liu, Guanglong Ding, Ye Zhou, Su-Ting Han, Guosheng Wang, Xiao Yu, Bing Chen, Zhufei Chu, Lunyao Wang, Yinshui Xia, Chen Mu, Feng Lin, Chixiao Chen, Bojun Cheng, Yannan Xing, Weitao Zeng, Hong Chen, Lei Yu, Giacomo Indiveri, Ning Qiao:
2022 roadmap on neuromorphic devices and applications research in China. Neuromorph. Comput. Eng. 2(4): 42501 (2022) - [j13]Zhufei Chu, Chuanhe Shang, Tingting Zhang, Yinshui Xia, Lunyao Wang, Weiqiang Liu:
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 30(12): 1827-1839 (2022) - 2021
- [j12]Zhufei Chu, Zeqiang Li, Yinshui Xia, Lunyao Wang, Weiqiang Liu:
BCD Adder Designs Based on Three-Input XOR and Majority Gates. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1942-1946 (2021) - 2020
- [j11]Zhufei Chu, Huiming Tian, Zeqiang Li, Yinshui Xia, Lun-Yao Wang:
A High-Performance Design of Generalized Pipeline Cellular Array. IEEE Comput. Archit. Lett. 19(1): 47-50 (2020) - [j10]Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli:
Advanced Functional Decomposition Using Majority and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1621-1634 (2020)
2010 – 2019
- 2019
- [j9]Zhufei Chu, Lei Shi, Lun-Yao Wang, Yinshui Xia:
Multi-objective algebraic rewriting in XOR-majority graphs. Integr. 69: 40-49 (2019) - [c9]Yichen Wang, Lunyao Wang:
Power optimization for FPRM logic using approximate computing technique. ASICON 2019: 1-4 - [c8]Qiuhong Ying, Lun-Yao Wang, Zhufei Chu, Yinshui Xia:
Area Optimization of MPRM Circuits Using Approximate Computing. ASICON 2019: 1-4 - [c7]Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli:
Structural rewriting in XOR-majority graphs. ASP-DAC 2019: 663-668 - [c6]Zhufei Chu, Winston Haaswijk, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli:
Exact Synthesis of Boolean Functions in Majority-of-Five Forms. ISCAS 2019: 1-5 - 2016
- [j8]Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang:
Efficient power pad assignment for multi-voltage SoC and its application in floorplanning. Int. J. Circuit Theory Appl. 44(8): 1533-1550 (2016) - [j7]Zhufei Chu, Yinshui Xia, Lun-Yao Wang:
Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence. Integr. 52: 335-346 (2016) - 2014
- [j6]Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang:
Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine. Microelectron. J. 45(4): 382-393 (2014) - [c5]Zhufei Chu, Yinshui Xia, Lun-Yao Wang:
Level shifter planning for timing constrained multi-voltage SoC floorplanning. ACM Great Lakes Symposium on VLSI 2014: 329-334 - 2013
- [j5]Lun-Yao Wang, Zhufei Chu, Yinshui Xia:
Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization. J. Comput. Sci. Technol. 28(6): 1054-1062 (2013) - [c4]Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang:
Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs. CAD/Graphics 2013: 87-94 - [c3]Lun-Yao Wang, Yinshui Xia:
Logic Minimization Based on Dual Logic. CAD/Graphics 2013: 115-122 - 2012
- [j4]Zhufei Chu, Yinshui Xia, Lun-Yao Wang:
Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm. J. Comput. Sci. Technol. 27(1): 113-120 (2012) - 2011
- [j3]Lun-Yao Wang, Yinshui Xia, Xiexiong Chen, A. E. A. Almaini:
Reed-Muller function optimization techniques with onset table. J. Zhejiang Univ. Sci. C 12(4): 288-296 (2011) - 2010
- [c2]Zhufei Chu, Yinshui Xia, William N. N. Hung, Lun-Yao Wang, Xiaoyu Song:
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping. DSD 2010: 681-688
2000 – 2009
- 2005
- [j2]Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini:
A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock. J. Comput. Sci. Technol. 20(2): 237-242 (2005) - [j1]Yinshui Xia, Lun-Yao Wang, Zong-Gang Zhou, Xien Ye, Jianping Hu:
Novel Synthesis and Optimization of Multi-Level Mixed Polarity Reed-Muller Functions. J. Comput. Sci. Technol. 20(6): 895-900 (2005) - [c1]Yinshui Xia, Xien Ye, Lun-Yao Wang, Zong-Gang Zhou:
Novel synthesis method of mixed polarity Reed-Muller functions. Circuits, Signals, and Systems 2005: 148-153
Coauthor Index
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