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2010 – 2019
- 2018
[c11]Frederick A. Ware, Javier Bueno, Liji Gopalakrishnan, Brent Haukness, Chris Haywood, Toni Juan, Eric Linstadt, Sally A. McKee, Steven C. Woo, Kenneth L. Wright, Craig Hampel, Gary Bronner:
Architecting a hardware-managed hybrid DIMM optimized for cost/performance. MEMSYS 2018: 327-340
2000 – 2009
- 2009
- [j3]Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan:
Larrabee: A Many-Core x86 Architecture for Visual Computing. IEEE Micro 29(1): 10-21 (2009) - [c10]Oscar Palomar
, Toni Juan, Juan J. Navarro:
Reusing cached schedules in an out-of-order processor with in-order issue logic. ICCD 2009: 246-253 - 2008
- [j2]Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan:
Larrabee: a many-core x86 architecture for visual computing. ACM Trans. Graph. 27(3): 18 (2008) - 2002
- [j1]Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan:
Asim: A Performance Model Framework. Computer 35(2): 68-76 (2002) - [c9]Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec:
Tarantula: A Vector Extension to the Alpha Architecture. ISCA 2002: 281-292 - 2001
- [c8]Yiannakis Sazeides, Toni Juan:
How to compare the performance of two SMT microarchitectures. ISPASS 2001: 180-183
1990 – 1999
- 1998
- [c7]Toni Juan, Sanji Sanjeevan, Juan J. Navarro:
Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction. ISCA 1998: 155-166 - [c6]Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan:
Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. MICRO 1998: 59-68 - 1997
- [c5]Toni Juan, Juan J. Navarro, Olivier Temam:
Data Caches for Superscalar Processors. International Conference on Supercomputing 1997: 60-67 - [c4]Toni Juan, Tomás Lang, Juan J. Navarro:
Reducing TLB power requirements. ISLPED 1997: 196-201 - 1996
- [c3]Juan J. Navarro, Elena García-Diego, Josep Lluís Larriba-Pey, Toni Juan:
Block Algorithms for Sparse Matrix Computations on High Performance Workstations. International Conference on Supercomputing 1996: 301-308 - [c2]Toni Juan, Tomás Lang, Juan J. Navarro:
The Difference-bit Cache. ISCA 1996: 114-120 - 1994
- [c1]Juan J. Navarro, Toni Juan, Tomás Lang:
MOB forms: a class of multilevel block algorithms for dense linear algebra operations. International Conference on Supercomputing 1994: 354-363
Coauthor Index
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