default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDYinyin Lin
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[c14]Zixu Li, Wang Wang, Xin Zhong, Manni Li, Jiayu Yang, Yinyin Lin, Guhyun Kim, Yosub Song, Chengchen Wang, Xiankui Xiong:
LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing. ISCAS 2024: 1-5- 2023
- [j16]Wang Wang
, Xin Zhong, Manni Li, Zixu Li, Yinyin Lin:
ANS: Assimilating Near Similarity at High Accuracy for Significant Deduction of CNN Storage and Computation. IEEE Access 11: 25415-25430 (2023) - 2022
- [j15]Yarong Fu, Wang Wang, Xin Zhong, Manni Li, Zixu Li, Qing Dong, Yu Jiang, Yinyin Lin:
Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5185-5194 (2022)
2010 – 2019
- 2017
- [j14]Yarong Fu, Kai Yang, B. A. Chen, Yinyin Lin:
3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance. Microelectron. J. 66: 1-8 (2017) - [j13]Weiliang Jing, Kai Yang, Yinyin Lin, Beomseop Lee, Sangkyu Yoon, Yong Ye, Yuan Du, Bomy Chen:
Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM. IEEE Trans. Computers 66(5): 912-918 (2017) - [j12]Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 186-190 (2017) - [c13]Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin:
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. ASICON 2017: 16-19 - [c12]Jianguo Yang, Yinyin Lin, Yarong Fu, Xiaoyong Xue, B. A. Chen:
A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application. ISCAS 2017: 1-4 - 2016
- [j11]Jianguo Yang, Xiaoyong Xue, Juan Xu, Fan Ye, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
A self-adaptive write driver with fast termination of step-up pulse for ReRAM. IEICE Electron. Express 13(7): 20160195 (2016) - [j10]Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu:
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 336-340 (2016) - [j9]Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1174-1178 (2016) - [c11]Yinyin Lin, Xinyi Hu, Jianguo Yang, Xiaoyong Xue:
A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG. ISCAS 2016: 13-16 - [c10]Yanqing Zhao, Juan Xu, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jaehwang Sim:
Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression. ISCAS 2016: 2807-2810 - 2015
- [c9]Jianguo Yang, Juan Xu, Bo Wang, Xiaoyong Xue, Ryan Huang, Qingtian Zou, Jingang Wu, Yinyin Lin:
A low cost and high reliability true random number generator based on resistive random access memory. ASICON 2015: 1-4 - [c8]Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae:
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. ASICON 2015: 1-4 - [c7]Yinyin Lin, Rui Yuan, Xiaoyong Xue, B. A. Chen:
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. ISCAS 2015: 377-380 - 2013
- [j8]Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. IEEE J. Solid State Circuits 48(5): 1315-1322 (2013) - [c6]Hui Li, Wei Zhu, Ningxi Liu, Cunlin Dong, Chao Meng, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM. ASICON 2013: 1-3 - [c5]Ningxi Liu, Yu Jiang, Qing Dong, Hui Li, Xinyi Hu, Yinyin Lin:
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing. ASICON 2013: 1-4 - [c4]Jianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin:
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. ASICON 2013: 1-4 - 2012
- [j7]Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin:
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express 9(12): 1051-1056 (2012) - [j6]Wenxiang Jian, Gang Jin, Na Yan, Zhongyu Bi, Hao Min, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Variation-tolerant CuxSiyO-based RRAM for low power application. IEICE Electron. Express 9(21): 1654-1659 (2012) - [c3]Xiaoyong Xue, W. X. Jian, Jianguo Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Yinyin Lin, R. Huang, Q. T. Zhou, J. G. Wu:
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. VLSIC 2012: 42-43 - 2011
- [j5]Xiaoyong Xue, Yufeng Xie, Yinyin Lin:
Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express 8(7): 454-459 (2011) - [c2]Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin:
A BIST scheme for high-speed Gain Cell eDRAM. ASICON 2011: 244-247 - [c1]Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin:
Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON 2011: 291-294 - 2010
- [j4]Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin:
A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. 93-C(12): 1692-1699 (2010)
2000 – 2009
- 2007
- [j3]Yang Hong, Yinyin Lin, Tingao Tang, Bomy Chen:
Multilevel Storage in Phase-Change Memory. IEICE Trans. Electron. 90-C(3): 634-640 (2007) - 2006
- [j2]Feifei Liao, Yiqing Ding, Yinyin Lin, Tingao Tang, Baowei Qiao, Yunfeng Lai, Jie Feng, Bomy Chen:
Characterization of Ge2Sb2Te5 thin film transistor and its application in non-volatile memory. Microelectron. J. 37(8): 841-844 (2006) - [j1]Hangbing Lv, Peng Zhou, Yinyin Lin, Tingao Tang, Baowei Qiao, Yunfeng Lai, Jie Feng, Bingchu Cai, Bomy Chen:
Electronic properties of GST for non-volatile memory. Microelectron. J. 37(9): 982-984 (2006)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-07-17 20:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
