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ORCIDTetsuro Itakura
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2020 – today
- 2022
[c27]Toshiki Sugimoto, Tuan Thanh Ta, Koichi Kokubun, Satoshi Kondo, Tetsuro Itakura, Hisaaki Katagiri, Yutaka Ota, Mitsuhiro Sengoku, Honam Kwon, Keita Sasaki, Hiroshi Kubota, Kazuhiro Suzuki, Katsuyuki Kimura, Akihide Sai:
1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation. VLSI Technology and Circuits 2022: 80-81
2010 – 2019
- 2019
- [j39]Kentaro Yoshioka
, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura:
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2575-2586 (2019) - 2017
- [c26]Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura:
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC 2017: 478-479 - 2016
- [j38]Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo:
A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(2): 547-554 (2016) - [j37]Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura:
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits 51(12): 3125-3136 (2016) - [c25]Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura:
20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting. A-SSCC 2016: 9-12 - [c24]Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura:
A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. ISCAS 2016: 482-485 - [c23]Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura:
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. ISSCC 2016: 122-123 - [c22]Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura:
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. ISSCC 2016: 336-337 - [c21]Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura:
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. ISSCC 2016: 436-437 - 2015
- [j36]Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura:
A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 492-499 (2015) - [c20]Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura:
A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. ISCAS 2015: 357-360 - 2014
- [c19]Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura:
A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. ISCAS 2014: 1151-1154 - [c18]Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura:
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. ISSCC 2014: 348-349 - 2013
- [j35]Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura:
A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1552-1561 (2013) - [j34]Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura:
All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1113-1121 (2013) - [c17]Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura:
A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. VLSI-DAT 2013: 1-4 - 2012
- [c16]Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura:
All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. ISCAS 2012: 1050-1053 - [c15]Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura:
A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. ISSCC 2012: 248-250 - 2011
- [j33]Masanori Furuta, Mai Nozawa, Tetsuro Itakura:
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. IEEE J. Solid State Circuits 46(6): 1360-1370 (2011) - [j32]Takafumi Yamaji, Hiroshi Tanimoto, Junya Matsuno, Tetsuro Itakura:
Harmonic Signal Rejection Schemes of Polyphase Downconverters. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(10): 2308-2317 (2011) - [j31]Ippei Akita, Tetsuro Itakura, Kei Shiraishi:
Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 724-728 (2011) - [c14]Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura:
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. A-SSCC 2011: 293-296 - [c13]Ippei Akita, Yuta Tsubouchi, Tetsuro Itakura, Michihiko Nishigaki, Hiroshi Uemura, Hideto Furuyama, Hideki Shibata:
A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS. ESSCIRC 2011: 343-346 - [c12]Akihide Sai, Takafumi Yamaji, Tetsuro Itakura:
A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. ISSCC 2011: 98-100 - [c11]Hiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki:
A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller. ISSCC 2011: 226-228 - 2010
- [j30]Tetsuro Itakura:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 355 (2010) - [j29]Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura:
A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 367-374 (2010) - [j28]Tomohiko Ito, Tetsuro Itakura:
A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 395-401 (2010) - [j27]Rui Ito, Tetsuro Itakura:
Phase Compensation Techniques for Low-Power Operational Amplifiers. IEICE Trans. Electron. 93-C(6): 730-740 (2010) - [c10]Masanori Furuta, Mai Nozawa, Tetsuro Itakura:
A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. ISSCC 2010: 382-383
2000 – 2009
- 2009
- [j26]Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura:
A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 411-420 (2009) - 2008
- [j25]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 454-460 (2008) - [j24]Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 557-560 (2008) - [j23]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. IEICE Trans. Electron. 91-C(6): 887-893 (2008) - [c9]Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura:
An area-efficient sampling rate converter using negative feedback technique. ISCAS 2008: 1922-1925 - 2007
- [j22]Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 365-371 (2007) - [j21]Osamu Watanabe, Rui Ito, Shigehito Saigusa, Tadashi Arai, Tetsuro Itakura:
A Fast fc Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems. IEICE Trans. Electron. 90-C(6): 1247-1252 (2007) - [j20]Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura:
A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. IEEE J. Solid State Circuits 42(11): 2326-2337 (2007) - [c8]Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura:
A novel quality factor tuning scheme for active-RC filters. ESSCIRC 2007: 496-499 - [c7]Hidenori Okuni, Rui Ito, Hiroshi Yoshida, Tetsuro Itakura:
A Direct Conversion Receiver with Fast-Settling DC Offset Canceller. PIMRC 2007: 1-5 - 2006
- [j19]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(7): 2003-2008 (2006) - [j18]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. Solid State Circuits 41(7): 1589-1595 (2006) - [c6]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. CICC 2006: 501-504 - [c5]Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni:
Balanced 3-phase analog signal processing for radio communications. ISCAS 2006 - 2005
- [j17]Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. IEICE Electron. Express 2(15): 429-433 (2005) - [j16]Takeshi Ueno, Tetsuro Itakura:
A 0.9 V 1.5 mW Continuous-Time Modulator for W-CDMA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(2): 461-468 (2005) - [j15]Rui Ito, Tetsuro Itakura, Tadashi Arai:
Phase Compensation Technique for a Low-Power Transconductor. IEICE Trans. Electron. 88-C(6): 1263-1266 (2005) - [j14]Hiroshi Yoshida, Takehiko Toyoda, Makoto Arai, Ryuichi Fujimoto, Toshiya Mitomo, Masato Ishii, Rui Ito, Tadashi Arai, Tetsuro Itakura, Hiroshi Tsurumi:
A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA. IEICE Trans. Electron. 88-C(6): 1271-1274 (2005) - [c4]Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS. CICC 2005: 747-750 - [c3]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. ESSCIRC 2005: 527-530 - 2004
- [j13]Tomohiko Ito, Takafumi Yamaji, Daisuke Kurose, Tetsuro Itakura:
Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design. IEICE Electron. Express 1(3): 63-68 (2004) - [j12]Shoji Otaka, Mitsuyuki Ashida, Masato Ishii, Tetsuro Itakura:
A +10-dBm IIP3 SiGe mixer with IM3 cancellation technique. IEEE J. Solid State Circuits 39(12): 2333-2341 (2004) - 2003
- [j11]Toshiyuki Umeda, Shoji Otaka, Kenji Kojima, Tetsuro Itakura:
A 1-V 2-GHz CMOS Up-Converter Using Self-Switching Mixers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 262-267 (2003) - [j10]Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda:
A 402-output TFT-LCD driver IC with power control based on the number of colors selected. IEEE J. Solid State Circuits 38(3): 503-510 (2003) - [j9]Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi, Tetsuro Itakura:
A four-input beam-forming downconverter for adaptive antennas. IEEE J. Solid State Circuits 38(10): 1619-1625 (2003) - 2002
- [j8]Osamu Watanabe, Takafumi Yamaji, Tetsuro Itakura, Ichiro Hattori:
A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 286-292 (2002) - [j7]Tetsuro Itakura, Hironori Minamizaki:
A Two-Gain-Stage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(8): 1913-1920 (2002) - [j6]Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura:
A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range. IEEE J. Solid State Circuits 37(5): 553-558 (2002) - [j5]Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura:
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. IEEE J. Solid State Circuits 37(7): 809-816 (2002) - [c2]Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda:
A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors. CICC 2002: 257-260
1990 – 1999
- 1999
- [j4]Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu:
A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. IEEE J. Solid State Circuits 34(8): 1155-1159 (1999) - [c1]Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Tadashi Arai:
A 2 Vpp linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF. CICC 1999: 509-512 - 1996
- [j3]Tetsuro Itakura, Tetsuya Iida:
A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier. IEEE J. Solid State Circuits 31(6): 847-849 (1996) - [j2]Hiroshi Tanimoto, Tetsuro Itakura, Takashi Ueno, Akira Yasuda, Kazuhiro Oda:
An offset-free LPF for π/4-shift QPSK signal generator. IEEE J. Solid State Circuits 31(12): 2051-2055 (1996) - 1995
- [j1]Takeshi Shima, Tetsuro Itakura, Shigeru Yamada, Hironori Minamizaki, Takeshi Ishioka:
Principle and applications of an autocharge-compensated sample and hold circuit. IEEE J. Solid State Circuits 30(8): 906-912 (1995)
Coauthor Index
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