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ORCIDValeria Bertacco
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- affiliation: University of Michigan, Ann Arbor, USA
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2020 – today
- 2024
[j28]Andy D. Pimentel
, Valeria Bertacco, Aida Todri-Sanial, Theocharis Theocharides:
DATE 2024: Consolidating the New Conference Format. IEEE Des. Test 41(5): 87-94 (2024)- [c135]Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
Duet: A Collaborative User Driven Recommendation System for Edge Devices. DAC 2024: 55:1-55:6 - [c134]Tersiteab Adem, Andrew McCrabb, Vidushi Goyal, Valeria Bertacco:
Evergreen: Comprehensive Carbon Model for Performance-Emission Tradeoffs. IISWC 2024: 132-143 - 2023
- [j27]Ian O'Connor, Robert Wille, Andy D. Pimentel, Valeria Bertacco:
Postpandemic Conferences: The DATE 2023 Experience. IEEE Des. Test 40(5): 104-112 (2023) - [c133]Andrew McCrabb, Aymen Ahmed, Valeria Bertacco:
ACRE: Accelerating Random Forests for Explainability. MICRO 2023: 1016-1028 - [i2]Young Geun Kim, Udit Gupta, Andrew McCrabb, Yonglak Son, Valeria Bertacco, David Brooks, Carole-Jean Wu:
GreenScale: Carbon-Aware Systems for Edge Computing. CoRR abs/2304.00404 (2023) - 2022
- [j26]Doowon Lee, Valeria Bertacco:
Bypassing Multicore Memory Bugs With Coarse-Grained Reconfigurable Logic. IEEE Trans. Computers 71(9): 2191-2204 (2022) - [j25]Vidushi Goyal, Reetuparna Das, Valeria Bertacco:
Hardware-friendly User-specific Machine Learning for Edge Devices. ACM Trans. Embed. Comput. Syst. 21(5): 62:1-62:29 (2022) - [c132]Nicholas Wendt, Todd M. Austin, Valeria Bertacco:
PriMax: maximizing DSL application performance with selective primitive acceleration. DAC 2022: 139-144 - [c131]Andrew McCrabb, Hellina Nigatu, Absalat Getachew, Valeria Bertacco:
DyGraph: a dynamic graph generator and benchmark suite. GRADES-NDA@SIGMOD 2022: 7:1-7:8 - 2021
- [j24]Andrew McCrabb, Valeria Bertacco:
Optimizing Vertex Pressure Dynamic Graph Partitioning in Many-Core Systems. IEEE Trans. Computers 70(6): 936-949 (2021) - [c130]Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
MyML: User-Driven Machine Learning. DAC 2021: 145-150 - [c129]Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das:
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM 2021: 88-96 - [c128]Austin Harris, Tarunesh Verma, Shijia Wei, Lauren Biernacki, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari, Todd M. Austin:
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. HOST 2021: 226-238 - [c127]Todd M. Austin, Austin Harris, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari:
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. HCS 2021: 1-18 - [c126]Pete Ehrett, Todd M. Austin, Valeria Bertacco:
Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets. ICCD 2021: 395-399 - [c125]Pete Ehrett, Nathan Block, Bing Schaefer, Adrian Berding, John Paul Koenig, Pranav Srinivasan, Valeria Bertacco, Todd M. Austin:
A Defense-Inspired Benchmark Suite. ISPASS 2021: 79-80 - [c124]Hiwot Tadese Kassa, Tarunesh Verma, Todd M. Austin, Valeria Bertacco:
ChipAdvisor: A Machine Learning Approach for Mapping Applications to Heterogeneous Systems. ISQED 2021: 292-299 - 2020
- [j23]Abraham Addisie, Valeria Bertacco:
Collaborative Accelerators for Streamlining MapReduce on Scale-up Machines With Incremental Data Aggregation. IEEE Trans. Computers 69(8): 1233-1247 (2020) - [c123]Abraham Addisie, Valeria Bertacco:
Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics. DAC 2020: 1-6 - [c122]Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning. DAC 2020: 1-19 - [c121]Leul Belayneh, Valeria Bertacco:
GraphVine: Exploiting Multicast for Scalable Graph Analytics. DATE 2020: 762-767 - [c120]Lauren Biernacki, Mark Gallagher, Valeria Bertacco, Todd M. Austin:
Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces. HOST 2020: 57-68 - [c119]Vidushi Goyal, Xiaowei Wang, Valeria Bertacco, Reetuparna Das:
Neksus: An Interconnect for Heterogeneous System-In-Package Architectures. IPDPS 2020: 12-21
2010 – 2019
- 2019
- [c118]Abraham Addisie, Valeria Bertacco:
Collaborative accelerators for in-memory MapReduce on scale-up machines. ASP-DAC 2019: 747-753 - [c117]Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd M. Austin:
Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. ASPLOS 2019: 469-484 - [c116]Andrew McCrabb, Eric Winsor, Valeria Bertacco:
DREDGE: Dynamic Repartitioning during Dynamic Graph Execution. DAC 2019: 28 - [c115]Pete Ehrett, Todd M. Austin, Valeria Bertacco:
SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design. DATE 2019: 510-515 - [c114]Leul Belayneh, Abraham Addisie, Valeria Bertacco:
MessageFusion: On-path Message Coalescing for Energy Efficient and Scalable Graph Analytics. ISLPED 2019: 1-6 - 2018
- [c113]Alessandro Danese, Valeria Bertacco, Graziano Pravadelli:
Symbolic assertion mining for security validation. DATE 2018: 1550-1555 - [c112]Todd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari:
Vulnerability-tolerant secure architectures. ICCAD 2018: 46 - [c111]Timothy Linscott, Pete Ehrett, Valeria Bertacco, Todd M. Austin:
SWAN: mitigating hardware trojans with design ambiguity. ICCAD 2018: 91 - [c110]Doowon Lee, Opeoluwa Matthews, Valeria Bertacco:
Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems. ICCD 2018: 17-25 - [c109]Abraham Addisie, Hiwot Kassa, Opeoluwa Matthews, Valeria Bertacco:
Heterogeneous Memory Subsystem for Natural Graph Analytics. IISWC 2018: 134-145 - 2017
- [c108]Fitsum Assamnew Andargie, Jonathan Rose, Todd M. Austin, Valeria Bertacco:
Energy efficient object detection on the mobile GP-GPU. AFRICON 2017: 945-950 - [c107]Biruk Mammo, Doowon Lee, Harrison Davis, Yijun Hou, Valeria Bertacco:
AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs. ASP-DAC 2017: 45-50 - [c106]Alessandro Danese, Graziano Pravadelli, Valeria Bertacco:
DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress). CODES+ISSS 2017: 9:1-9:2 - [c105]Javad Bagherzadeh, Valeria Bertacco:
3DFAR: A three-dimensional fabric for reliable multi-core processors. DATE 2017: 310-313 - [c104]Ofir Weisse, Valeria Bertacco, Todd M. Austin:
Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves. ISCA 2017: 81-93 - [c103]Doowon Lee, Valeria Bertacco:
MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation. ISCA 2017: 201-213 - [c102]Evan Chavis, Harrison Davis, Yijun Hou, Matthew Hicks, Salessawi Ferede Yitbarek, Todd M. Austin, Valeria Bertacco:
SNIFFER: A high-accuracy malware detector for enterprise-based systems. IVSW 2017: 70-75 - 2016
- [j22]Ritesh Parikh, Valeria Bertacco:
Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults. IEEE Trans. Computers 65(7): 2241-2256 (2016) - [c101]Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco:
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. DAC 2016: 24:1-24:6 - [c100]Rawan Abdel-Khalek, Valeria Bertacco:
Correct runtime operation for NoCs through adaptive-region protection. DATE 2016: 1189-1194 - [c99]Biruk Mammo, Milind Furia, Valeria Bertacco, Scott A. Mahlke, Daya Shanker Khudia:
BugMD: automatic mismatch diagnosis for bug triaging. ICCAD 2016: 117 - 2015
- [j21]Biruk W. Mammo, Valeria Bertacco, Andrew DeOrio, Ilya Wagner:
Post-Silicon Validation of Multiprocessor Memory Consistency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 1027-1037 (2015) - [c98]Valeria Bertacco, Wade Bonkowski:
ItHELPS: Iterative high-accuracy error localization in post-silicon. ICCD 2015: 196-199 - [c97]Biruk Mammo, Ritesh Parikh, Valeria Bertacco:
ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability. ISLPED 2015: 297-302 - [c96]Vaibhav Gogte, Doowon Lee, Ritesh Parikh, Valeria Bertacco:
NoCVision: A Network-on-Chip Dynamic Visualization Solution. NoCArc@MICRO 2015: 21-26 - [c95]Doowon Lee, Ritesh Parikh, Valeria Bertacco:
Highly Fault-tolerant NoC Routing with Application-aware Congestion Management. NOCS 2015: 10:1-10:8 - [c94]Valeria Bertacco:
Panel: When will the cost of dependability end innovation in computer design? VTS 2015: 1 - 2014
- [j20]Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini:
At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs. IEEE Trans. Computers 63(3): 703-717 (2014) - [j19]Andrea Pellegrini, Valeria Bertacco:
Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 265-278 (2014) - [j18]Ritesh Parikh, Valeria Bertacco:
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality. ACM Trans. Embed. Comput. Syst. 13(3s): 104:1-104:30 (2014) - [j17]Rawan Abdel-Khalek, Valeria Bertacco:
Post-silicon platform for the functional diagnosis and debug of networks-on-chip. ACM Trans. Embed. Comput. Syst. 13(3s): 112:1-112:25 (2014) - [c93]Ritesh Parikh, Reetuparna Das, Valeria Bertacco:
Power-Aware NoCs through Routing and Topology Reconfiguration. DAC 2014: 162:1-162:6 - [c92]Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco:
ArChiVED: Architectural checking via event digests for high performance validation. DATE 2014: 1-6 - [c91]Doowon Lee, Ritesh Parikh, Valeria Bertacco:
Brisk and limited-impact NoC routing reconfiguration. DATE 2014: 1-6 - [c90]Animesh Jain, Ritesh Parikh, Valeria Bertacco:
High-radix on-chip networks with low-radix routers. ICCAD 2014: 289-294 - [c89]Rawan Abdel-Khalek, Valeria Bertacco:
DiAMOND: Distributed alteration of messages for on-chip network debug. NOCS 2014: 127-134 - 2013
- [c88]William Arthur, Biruk Mammo, Ricardo Rodríguez Jorge, Todd M. Austin, Valeria Bertacco:
Schnauzer: scalable profiling for likely security bug sites. CGO 2013: 24:1-24:11 - [c87]Andrew DeOrio, Qingkun Li, Matthew Burgess, Valeria Bertacco:
Machine learning-based anomaly detection for post-silicon bug diagnosis. DATE 2013: 491-496 - [c86]Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, Hiren D. Patel:
On the use of GP-GPUs for accelerating compute-intensive EDA applications. DATE 2013: 1357-1366 - [c85]Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco:
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms. ICCAD 2013: 311-317 - [c84]Ritesh Parikh, Valeria Bertacco:
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults. MICRO 2013: 148-159 - [c83]Andrea Pellegrini, Valeria Bertacco:
Cobra: A comprehensive bundle-based reliable architecture. ICSAMOS 2013: 247-254 - [e1]Valeria Bertacco, Axel Legay:
Hardware and Software: Verification and Testing - 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings. Lecture Notes in Computer Science 8244, Springer 2013, ISBN 978-3-319-03076-0 [contents] - 2012
- [j16]Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David T. Blaauw, Jin Hu, Gregory K. Chen:
A Reliable Routing Architecture and Algorithm for NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 726-739 (2012) - [c82]Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee:
SystemC simulation on GP-GPUs: CUDA vs. OpenCL. CODES+ISSS 2012: 343-352 - [c81]Sara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi:
SAGA: SystemC acceleration on GPU architectures. DAC 2012: 115-120 - [c80]Valeria Bertacco:
Humans for EDA and EDA for humans. DAC 2012: 729-733 - [c79]Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco:
Checking architectural outputs instruction-by-instruction on acceleration platforms. DAC 2012: 955-961 - [c78]Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco:
Approximating checkers for simulation acceleration. DATE 2012: 153-158 - [c77]Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco:
CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. DATE 2012: 1106-1109 - [c76]Andrew DeOrio, Jialin Li, Valeria Bertacco:
Bridging pre- and post-silicon debugging with BiPeD. ICCAD 2012: 95-100 - [c75]Rawan Abdel-Khalek, Valeria Bertacco:
Functional post-silicon diagnosis and debug for networks-on-chip. ICCAD 2012: 557-563 - [c74]Andrea Pellegrini, Joseph L. Greathouse, Valeria Bertacco:
Viper: Virtual pipelines for enhanced reliability. ISCA 2012: 344-355 - [c73]Biruk Mammo, Jim Larimer, Matthew Morgan, Dave Fan, Eric Hennenhoefer, Valeria Bertacco:
Architectural Trace-Based Functional Coverage for Multiprocessor Verification. MTV 2012: 1-5 - [c72]Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco:
Comprehensive online defect diagnosis in on-chip networks. VTS 2012: 44-49 - 2011
- [j15]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Gate-Level Simulation with GPU Computing. ACM Trans. Design Autom. Electr. Syst. 16(3): 30:1-30:26 (2011) - [c71]Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco:
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment. PACT 2011: 298-309 - [c70]Joseph L. Greathouse, Chelsea LeBlanc, Todd M. Austin, Valeria Bertacco:
Highly scalable distributed dataflow analysis. CGO 2011: 277-288 - [c69]Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh:
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips. DAC 2011: 912-917 - [c68]Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini:
ReliNoC: A reliable network for priority-based on-chip communication. DATE 2011: 667-672 - [c67]Andrea Pellegrini, Valeria Bertacco:
Cardio: Adaptive CMPs for reliability through dynamic introspective operation. HLDVT 2011: 98-105 - [c66]Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco:
Simulation-based signal selection for state restoration in silicon debug. ICCAD 2011: 595-601 - [c65]Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco:
Post-silicon bug diagnosis with inconsistent executions. ICCAD 2011: 755-761 - [c64]Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco:
Functional correctness for CMP interconnects. ICCD 2011: 352-359 - [c63]Ritesh Parikh, Valeria Bertacco:
Formally enhanced runtime verification to ensure NoC functional correctness. MICRO 2011: 410-419 - [c62]Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini:
A distributed and topology-agnostic approach for on-line NoC testing. NOCS 2011: 113-120 - 2010
- [j14]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko:
Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. 15(3): 26:1-26:24 (2010) - [c61]Valeria Bertacco:
Post-silicon debugging for multi-core designs. ASP-DAC 2010: 255-258 - [c60]Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor:
Bridging pre-silicon verification and post-silicon validation. DAC 2010: 94-95 - [c59]Andrew DeOrio, Valeria Bertacco:
Electronic design automation for social networks. DAC 2010: 621-622 - [c58]Andrea Pellegrini, Valeria Bertacco, Todd M. Austin:
Fault-based attack of RSA authentication. DATE 2010: 855-860 - [c57]Valeria Bertacco:
Verification Failures: What to Do When Things Go Wrong. Haifa Verification Conference 2010: 23 - [c56]Andrea Pellegrini, Valeria Bertacco:
Application-Aware diagnosis of runtime hardware faults. ICCAD 2010: 487-492 - [c55]Debapriya Chatterjee, Valeria Bertacco:
EQUIPE: Parallel equivalence checking with GP-GPUs. ICCD 2010: 486-493 - [c54]Rawan Abdel-Khalek, Valeria Bertacco:
SoCGuard: A runtime verification solution for the functional correctness of SoCs. VLSI-SoC 2010: 49-54
2000 – 2009
- 2009
- [b2]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair. Lecture Notes in Electrical Engineering 32, Springer 2009, ISBN 978-1-4020-9364-7, pp. 3-185 [contents] - [j13]Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco:
Incremental Verification with Error Detection, Diagnosis, and Visualization. IEEE Des. Test Comput. 26(2): 34-43 (2009) - [j12]Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco:
A Flexible Software-Based Framework for Online Detection of Hardware Defects. IEEE Trans. Computers 58(8): 1063-1079 (2009) - [j11]Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen:
Inferno: Streamlining Verification With Inferred Semantics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 728-741 (2009) - [c53]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Event-driven gate-level simulation with GP-GPUs. DAC 2009: 557-562 - [c52]Andrew DeOrio, Valeria Bertacco:
Human computing for EDA. DAC 2009: 621-622 - [c51]Valeria Bertacco:
Debugging strategies for mere mortals. DAC 2009: 635-638 - [c50]David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester:
Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817 - [c49]David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David T. Blaauw:
A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26 - [c48]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Customizing IP cores for system-on-chip designs using extensive external don't-cares. DATE 2009: 582-585 - [c47]Ilya Wagner, Valeria Bertacco:
Caspar: Hardware patching for multicore processors. DATE 2009: 658-663 - [c46]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
GCS: High-performance gate-level simulation with GPGPUs. DATE 2009: 1332-1337 - [c45]J. Hao, Valeria Bertacco:
PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. HLDVT 2009: 54-59 - [c44]Debapriya Chatterjee, Valeria Bertacco:
Activity-based refinement for abstraction-guided simulation. HLDVT 2009: 146-153 - [c43]Andrew DeOrio, Ilya Wagner, Valeria Bertacco:
Dacota: Post-silicon validation of the memory subsystem in multi-core designs. HPCA 2009: 405-416 - [i1]Bernd Becker, Valeria Bertacco, Rolf Drechsler, Masahiro Fujita:
09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers. Algorithms and Applications for Next Generation SAT Solvers 2009 - 2008
- [j10]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Automating Postsilicon Debugging and Repair. Computer 41(7): 47-54 (2008) - [j9]Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao:
Reliable Systems on Unreliable Fabrics. IEEE Des. Test Comput. 25(4): 322-332 (2008) - [j8]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
SafeResynth: A new technique for physical synthesis. Integr. 41(4): 544-556 (2008) - [j7]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors With Counterexamples and Resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 184-188 (2008) - [j6]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 380-393 (2008) - [j5]Stephen Plaza, Igor L. Markov, Valeria Bertacco:
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2107-2119 (2008) - [c42]Stephen Plaza, Igor L. Markov, Valeria Bertacco:
Random Stimulus Generation using Entropy and XOR Constraints. DATE 2008: 664-669 - [c41]Ilya Wagner, Valeria Bertacco:
MCjammer: Adaptive Verification for Multi-core Designs. DATE 2008: 670-675 - [c40]Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg:
Panel: Software practices for verification/testbench management. HLDVT 2008: 35-37 - [c39]Ilya Wagner, Valeria Bertacco:
Reversi: Post-silicon validation system for modern microprocessors. ICCD 2008: 307-314 - [c38]Andrew DeOrio, Adam Bauserman, Valeria Bertacco:
Post-silicon verification for cache coherence. ICCD 2008: 348-355 - [c37]Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin:
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. ICCD 2008: 363-370 - [c36]Stephen Plaza, Igor L. Markov, Valeria Bertacco:
Optimizing non-monotonic interconnect using functional simulation and logic restructuring. ISPD 2008: 95-102 - [c35]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Reap what you sow: spare cells for post-silicon metal fix. ISPD 2008: 103-110 - [c34]Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie:
Testudo: Heavyweight security analysis via statistical sampling. MICRO 2008: 117-128 - 2007
- [j4]Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky:
Architecting a reliable CMP switch architecture. ACM Trans. Archit. Code Optim. 4(1): 2 (2007) - [j3]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Simulation-Based Bug Trace Minimization With BMC-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 152-165 (2007) - [j2]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Microprocessor Verification via Feedback-Adjusted Markov Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1126-1138 (2007) - [j1]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Postplacement rewiring by exhaustive search for functional symmetries. ACM Trans. Design Autom. Electr. Syst. 12(3): 32:1-32:21 (2007) - [c33]Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Node Mergers in the Presence of Don't Cares. ASP-DAC 2007: 414-419 - [c32]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Safe Delay Optimization for Physical Synthesis. ASP-DAC 2007: 628-633 - [c31]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors with Counterexamples and Resynthesis. ASP-DAC 2007: 944-949 - [c30]Ilya Wagner, Valeria Bertacco:
Engineering trust with semantic guardians. DATE 2007: 743-748 - [c29]Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin:
Low-cost protection for SER upsets and silicon defects. DATE 2007: 1146-1151 - [c28]Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov:
Automatic error diagnosis and correction for RTL designs. HLDVT 2007: 65-72 - [c27]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Automating post-silicon debugging and repair. ICCAD 2007: 91-98 - [c26]Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco:
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. ISQED 2007: 487-494 - [c25]Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco:
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. MICRO 2007: 97-108 - [c24]Andrew DeOrio, Adam Bauserman, Valeria Bertacco:
Chico: An On-chip Hardware Checker for Pipeline Control Logic. MTV 2007: 91-97 - 2006
- [b1]Valeria Bertacco:
Scalable Hardware Verification with Symbolic Simulation. Springer 2006, ISBN 978-0-387-24411-2, pp. I-XX, 1-177 - [c23]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Depth-driven verification of simultaneous interfaces. ASP-DAC 2006: 442-447 - [c22]Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin:
Ultra low-cost defect protection for microprocessor pipelines. ASPLOS 2006: 73-82 - [c21]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Shielding against design flaws with field repairable control logic. DAC 2006: 344-347 - [c20]Smitha Shyam, Valeria Bertacco:
Distance-guided hybrid verification with GUIDO. DATE 2006: 1211-1216 - [c19]Valeria Bertacco:
Distance-Guided Hybrid Verification with GUIDO. HLDVT 2006: 151 - [c18]Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky:
BulletProof: a defect-tolerant CMP switch architecture. HPCA 2006: 5-16 - [c17]Beth Isaksen, Valeria Bertacco:
Verification through the principle of least astonishment. ICCAD 2006: 860-867 - [c16]Valeria Bertacco:
Formal verification for real-world designs. SBCCI 2006: 5 - [c15]Valeria Bertacco:
Low maintenance verification. SBCCI 2006: 12 - 2005
- [c14]Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge:
Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7 - [c13]Stephen Plaza, Valeria Bertacco:
STACCATO: disjoint support decompositions from BDDs through symbolic kernels. ASP-DAC 2005: 276-279 - [c12]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
StressTest: an automatic approach to test generation via activity monitors. DAC 2005: 783-788 - [c11]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. ICCAD 2005: 56-63 - [c10]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Simulation-based bug trace minimization with BMC-based refinement. ICCAD 2005: 1045-1051 - [c9]Todd M. Austin, Valeria Bertacco:
Deployment of Better Than Worst-Case Design: Solutions and Needs. ICCD 2005: 550-558 - 2004
- [c8]Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge:
Circuit-aware architectural simulation. DAC 2004: 305-310 - [c7]Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge:
Microarchitectural power modeling techniques for deep sub-micron microprocessors. ISLPED 2004: 212-217 - 2002
- [c6]Valeria Bertacco, Kunle Olukotun:
Efficient state representation for symbolic simulation. DAC 2002: 99-104 - 2000
- [c5]Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long:
Smart Simulation Using Collaborative Formal and Simulation Engines. ICCAD 2000: 120-126
1990 – 1999
- 1999
- [c4]Valeria Bertacco, Maurizio Damiani, Stefano Quer:
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. DAC 1999: 391-396 - 1997
- [c3]Valeria Bertacco, Maurizio Damiani:
The disjunctive decomposition of logic functions. ICCAD 1997: 78-82 - 1996
- [c2]Valeria Bertacco, Maurizio Damiani:
Boolean Function Representation Using Parallel-Access Diagrams. Great Lakes Symposium on VLSI 1996: 112-117 - [c1]Valeria Bertacco, Maurizio Damiani:
Boolean Function Representation Based on Disjoint-Support Decompositions. ICCD 1996: 27-32
Coauthor Index
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