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ORCIDThilo Pionteck
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- affiliation: University of Lübeck, Germany
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2020 – today
- 2024
[c90]Daniele Passaretti
, Thilo Pionteck:
On-the-Fly CT Image Pre-processing on MPSoC-FPGAs. ARCS 2024: 177-191- [c89]Victor Van Wijhe, Vincent Sprave, Daniele Passaretti, Nikolaos Alachiotis, Gerrit Grutzeck, Thilo Pionteck, Steven van der Vlugt:
Exploring the Versal AI Engines for Signal Processing in Radio Astronomy. FPL 2024: 1-10 - [c88]Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck:
An Architectural Template for FPGA Overlays Targeting Data Flow Applications. IPDPS (Workshops) 2024: 162-168 - [c87]Max Tzschoppe, Daniele Passaretti, Amir Najafi, Sebastian Fischer, Martin Wilhelm, Alberto García-Ortiz, Thilo Pionteck:
Impact of Wave Pipelining on NoCs for Heterogeneous Monolithic 3D SoCs. MOCAST 2024: 1-6 - [c86]Gerald Krell, Thilo Pionteck:
Large Filter Low-Level Processing by Edge TPU. VISIGRAPP (3): VISAPP 2024: 464-473 - [e9]Dietmar Fey, Benno Stabernack, Stefan Lankes, Mathias Pacher, Thilo Pionteck:
Architecture of Computing Systems - 37th International Conference, ARCS 2024, Potsdam, Germany, May 14-16, 2024, Proceedings. Lecture Notes in Computer Science 14842, Springer 2024, ISBN 978-3-031-66145-7 [contents] - 2023
- [j23]Daniele Passaretti, Max Steiger, Thilo Pionteck:
Enabling Plug-and-Play in Cyber-Physical Systems Using MPSoC-FPGAs. IEEE Access 11: 116219-116234 (2023) - [j22]Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck:
A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units. Concurr. Comput. Pract. Exp. 35(25) (2023) - [j21]Bala Gurumurthy, David Broneske, Martin Schäler, Thilo Pionteck, Gunter Saake:
Novel insights on atomic synchronization for sort-based group-by on GPUs. Distributed Parallel Databases 41(3): 387-409 (2023) - [j20]Tobias Groth, Sven Groppe, Thilo Pionteck, Franz Valdiek, Martin Koppehel:
Hybrid CPU/GPU/APU accelerated query, insert, update and erase operations in hash tables with string keys. Knowl. Inf. Syst. 65(10): 4359-4377 (2023) - [c85]Bala Gurumurthy, Vasudev Raghavendra Bidarkar, David Broneske, Thilo Pionteck, Gunter Saake:
What Happens When Two Multi-Query Optimization Paradigms Combine? - A Hybrid Shared Sub-Expression (SSE) and Materialized View Reuse (MVR) Study. ADBIS 2023: 74-87 - [c84]Vitalii Burtsev, Martin Wilhelm, Anna Drewes, Bala Gurumurthy, David Broneske, Thilo Pionteck, Gunter Saake:
FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing. ARC 2023: 115-130 - [c83]Daniele Passaretti, Thilo Pionteck:
A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography. ARC 2023: 361-365 - [c82]Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck:
A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing. FCCM 2023: 212 - [c81]Bala Gurumurthy, David Broneske, Gabriel Campero Durand, Thilo Pionteck, Gunter Saake:
ADAMANT: A Query Executor with Plug-In Interfaces for Easy Co-processor Integration. ICDE 2023: 1153-1166 - [e8]Georgios I. Goumas, Sven Tomforde, Jürgen Brehm, Stefan Wildermann, Thilo Pionteck:
Architecture of Computing Systems - 36th International Conference, ARCS 2023, Athens, Greece, June 13-15, 2023, Proceedings. Lecture Notes in Computer Science 13949, Springer 2023, ISBN 978-3-031-42784-8 [contents] - 2022
- [j19]Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García-Ortiz, Thilo Pionteck:
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs. ACM Trans. Model. Comput. Simul. 32(1): 3:1-3:21 (2022) - [c80]Daniele Passaretti, Felix Boehm, Martin Wilhelm, Thilo Pionteck:
Hardware Isolation Support for Low-Cost SoC-FPGAs. ARCS 2022: 148-163 - [c79]Tobias Groth, Sven Groppe, Thilo Pionteck, Franz Valdiek, Martin Koppehel:
Accelerated Parallel Hybrid GPU/CPU Hash Table Queries with String Keys. DEXA (2) 2022: 191-203 - [c78]Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck:
Modeling Task Mapping for Data-Intensive Applications in Heterogeneous Systems. Euro-Par Workshops 2022: 145-157 - [e7]Martin Schulz, Carsten Trinitis, Nikela Papadopoulou, Thilo Pionteck:
Architecture of Computing Systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022, Proceedings. Lecture Notes in Computer Science 13642, Springer 2022, ISBN 978-3-031-21866-8 [contents] - [i5]Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck:
Modeling Task Mapping for Data-intensive Applications in Heterogeneous Systems. CoRR abs/2208.06321 (2022) - 2021
- [j18]David Broneske, Anna Drewes, Bala Gurumurthy, Imad Hajjar, Thilo Pionteck, Gunter Saake:
In-Depth Analysis of OLAP Query Performance on Heterogeneous Hardware. Datenbank-Spektrum 21(2): 133-143 (2021) - [c77]Christopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck:
StreamGrid - An AXI-Stream-Compliant Overlay Architecture. ARC 2021: 156-170 - [c76]Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck:
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. ASP-DAC 2021: 197-203 - [c75]Daniele Passaretti, Thilo Pionteck:
Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography. FCCM 2021: 257 - [c74]Bala Gurumurthy, David Broneske, Martin Schäler, Thilo Pionteck, Gunter Saake:
An Investigation of Atomic Synchronization for Sort-Based Group-By Aggregation on GPUs. ICDE Workshops 2021: 48-53 - [c73]Martin Koppehel, Tobias Groth, Sven Groppe, Thilo Pionteck:
CuART - a CUDA-based, scalable Radix-Tree lookup and update engine. ICPP 2021: 12:1-12:10 - [c72]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED 2021: 60-66 - [c71]Anna Drewes, Martin Koppehel, Thilo Pionteck:
Dead-Ends in FPGAs for Database Acceleration. SAMOS 2021: 493-504 - [e6]Christian Hochberger, Lars Bauer, Thilo Pionteck:
Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 7-8, 2021, Proceedings. Lecture Notes in Computer Science 12800, Springer 2021, ISBN 978-3-030-81681-0 [contents] - 2020
- [j17]Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe:
Hardware-aided update acceleration in a hybrid Semantic Web database system. J. Supercomput. 76(10): 7961-7984 (2020) - [c70]Balasubramanian Gurumurthy, Imad Hajjar, David Broneske, Thilo Pionteck, Gunter Saake:
When Vectorwise Meets Hyper, Pipeline Breakers Become the Moderator. ADMS@VLDB 2020: 1-10 - [c69]Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck:
Optimising Operator Sets for Analytical Database Processing on FPGAs. ARC 2020: 30-44 - [c68]Michael Müller, Thomas Leich, Thilo Pionteck, Gunter Saake, Jens Teubner, Olaf Spinczyk:
He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware. ARCS 2020: 82-96 - [c67]Martin Koppehel, Thilo Pionteck:
Ultra-Low-Latency Video Encoding on Heterogenous Hardware Platforms. FPT 2020: 287 - [c66]Daniele Passaretti, Thilo Pionteck:
Hardware/Software Co-Design of a control and data acquisition system for Computed Tomography. MOCAST 2020: 1-4 - [c65]Tobias Groth, Sven Groppe, Martin Koppehel, Thilo Pionteck:
Parallelizing Approximate Search on Adaptive Radix Trees. SEBD 2020: 56-67 - [e5]André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis:
Architecture of Computing Systems - ARCS 2020 - 33rd International Conference, Aachen, Germany, May 25-28, 2020, Proceedings. Lecture Notes in Computer Science 12155, Springer 2020, ISBN 978-3-030-52793-8 [contents] - [i4]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR abs/2012.12563 (2020)
2010 – 2019
- 2019
- [j16]Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García Ortiz, Thilo Pionteck:
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. IEEE Access 7: 135145-135163 (2019) - [j15]Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz:
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. Integr. 67: 60-72 (2019) - [j14]Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz:
Simulation environment for link energy estimation in networks-on-chip with virtual channels. Integr. 68: 147-156 (2019) - [c64]Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck:
System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips. ICCD 2019: 409-412 - [c63]Daniele Passaretti, Jan Moritz Joseph, Thilo Pionteck:
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models. FPT 2019: 279-282 - [c62]Jan Moritz Joseph, Dominik Ermel, Tobias Drewes, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck:
Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips. MOCAST 2019: 1-4 - [e4]Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck:
Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings. Lecture Notes in Computer Science 11479, Springer 2019, ISBN 978-3-030-18655-5 [contents] - [i3]Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García-Ortiz, Thilo Pionteck:
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. CoRR abs/1909.04554 (2019) - [i2]Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck:
System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips. CoRR abs/1909.13807 (2019) - [i1]Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García Ortiz, Thilo Pionteck:
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs. CoRR abs/1912.05670 (2019) - 2018
- [j13]Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann:
Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum 18(3): 145-156 (2018) - [j12]Bala Gurumurthy, David Broneske, Tobias Drewes, Thilo Pionteck, Gunter Saake:
Cooking DBMS Operations using Granular Primitives - An Overview on a Primitive-based RDBMS Query Evaluation. Datenbank-Spektrum 18(3): 183-193 (2018) - [c61]Tobias Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck:
Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs. FPT 2018: 266-269 - [c60]Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck:
Hardware-Accelerated Index Construction for Semantic Web. FPT 2018: 278-281 - [c59]Bala Gurumurthy, Tobias Drewes, David Broneske, Gunter Saake, Thilo Pionteck:
Adaptive Data Processing in Heterogeneous Hardware Systems. Grundlagen von Datenbanken 2018: 10-15 - [c58]Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz:
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. PATMOS 2018: 222-228 - [c57]Jan Moritz Joseph, Lennart Bamberg, Gerald Krell, Imad Hajjar, Alberto García Ortiz, Thilo Pionteck:
Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. ReCoSoC 2018: 1-8 - [e3]Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck:
Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings. Lecture Notes in Computer Science 10793, Springer 2018, ISBN 978-3-319-77609-5 [contents] - 2017
- [j11]Jan Moritz Joseph, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck:
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. Microprocess. Microsystems 48: 36-47 (2017) - [j10]Stefan Werner, Dennis Heinrich, Thilo Pionteck, Sven Groppe:
Semi-static operator graphs for accelerated query execution on FPGAs. Microprocess. Microsystems 53: 178-189 (2017) - [c56]Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck:
Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications. ARCS 2017: 47-58 - [c55]Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck:
Continuous live-tracing as debugging approach on FPGAs. ReConFig 2017: 1-8 - [c54]Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck:
An FPGA-based prototyping framework for Networks-on-Chip. ReConFig 2017: 1-7 - [c53]Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck:
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. ReConFig 2017: 1-8 - [c52]Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto García Ortiz, Thilo Pionteck:
Design method for asymmetric 3D interconnect architectures with high level models. ReCoSoC 2017: 1-8 - [e2]Jens Knoop, Wolfgang Karl, Martin Schulz, Koji Inoue, Thilo Pionteck:
Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 3-6, 2017, Proceedings. Lecture Notes in Computer Science 10172, Springer 2017, ISBN 978-3-319-54998-9 [contents] - 2016
- [j9]Stefan Werner, Dennis Heinrich, Marc Stelzner, Volker Linnemann, Thilo Pionteck, Sven Groppe:
Accelerated join evaluation in Semantic Web databases by using FPGAs. Concurr. Comput. Pract. Exp. 28(7): 2031-2051 (2016) - [j8]Sven Groppe, Dennis Heinrich, Christopher Blochwitz, Thilo Pionteck:
Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders. Open J. Big Data 2(1): 11-25 (2016) - [j7]Stefan Werner, Dennis Heinrich, Sven Groppe, Christopher Blochwitz, Thilo Pionteck:
Runtime Adaptive Hybrid Query Engine based on FPGAs. Open J. Databases 3(1): 21-41 (2016) - [j6]Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck:
RAW 2014: Random Number Generators on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 9(2): 15:1-15:21 (2016) - [c51]Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck:
Adaptive allocation of default router paths in Network-on-Chips for latency reduction. HPCS 2016: 140-147 - [c50]Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck:
Hardware-accelerated pose estimation for embedded systems using Vivado HLS. ReConFig 2016: 1-7 - [c49]Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck:
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip. ReCoSoC 2016: 1-8 - [e1]Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich:
Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings. Lecture Notes in Computer Science 9637, Springer 2016, ISBN 978-3-319-30694-0 [contents] - 2015
- [j5]Sven Groppe, Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck:
PatTrieSort - External String Sorting based on Patricia Tries. Open J. Databases 2(1): 36-50 (2015) - [c48]Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz:
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. NORCAS 2015: 1-4 - [c47]Rico Backasch, Gerald Hempel, Christopher Blochwitz, Stefan Werner, Sven Groppe, Thilo Pionteck:
An architectural template for composing application specific datapaths at runtime. ReConFig 2015: 1-6 - [c46]Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe:
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. ReConFig 2015: 1-7 - [c45]Dennis Heinrich, Stefan Werner, Marc Stelzner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe:
Hybrid FPGA approach for a B+ tree in a Semantic Web database system. ReCoSoC 2015: 1-8 - [c44]Stefan Werner, Dennis Heinrich, Jannik Piper, Sven Groppe, Rico Backasch, Christopher Blochwitz, Thilo Pionteck:
Automated composition and execution of hardware-accelerated operator graphs. ReCoSoC 2015: 1-8 - 2014
- [c43]Stefan Werner, Dennis Heinrich, Marc Stelzner, Sven Groppe, Rico Backasch, Thilo Pionteck:
Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases. CIT 2014: 539-546 - [c42]Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck:
Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs. IPDPS Workshops 2014: 199-204 - [c41]Jan Moritz Joseph, Thilo Pionteck:
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling. ISSoC 2014: 1-6 - [c40]Rico Backasch, Gerald Hempel, Stefan Werner, Sven Groppe, Thilo Pionteck:
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation. ReConFig 2014: 1-6 - 2013
- [c39]Stefan Werner, Sven Groppe, Volker Linnemann, Thilo Pionteck:
Hardware-accelerated join processing in large Semantic Web databases with FPGAs. HPCS 2013: 131-138 - [c38]Thilo Pionteck, Christoph Osterloh:
Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems. HPCS 2013: 229-232 - [c37]Gerald Hempel, Jan Hoyer, Thilo Pionteck, Christian Hochberger:
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs. ReCoSoC 2013: 1-6 - 2012
- [c36]Volker Hampel, Thilo Pionteck, Erik Maehle:
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors. ARCS 2012: 160-171 - [c35]Christoph Osterloh, Thilo Pionteck, Erik Maehle:
MONSUN II: A small and inexpensive AUV for underwater swarms. ROBOTIK 2012 - 2011
- [c34]Thilo Pionteck, Christoph Osterloh, Carsten Albrecht:
Linking Formal Description and Simulation of Runtime Reconfigurable Systems. ReConFig 2011: 158-163 - 2010
- [c33]Thilo Pionteck, Werner Brockmann:
A concept of a trust management architecture to increase the robustness of nano age devices. DSN Workshops 2010: 142-147 - [c32]Thilo Pionteck, Steffen Sammann, Carsten Albrecht:
Optimizing Runtime Reconfiguration Decisions. EUC 2010: 39-46 - [p1]Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle, Thilo Pionteck:
DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors. Dynamically Reconfigurable Systems 2010: 335-354
2000 – 2009
- 2009
- [j4]Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle:
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime. Int. J. Reconfigurable Comput. 2009: 942930:1-942930:10 (2009) - 2008
- [j3]Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle:
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips. Parallel Process. Lett. 18(2): 275-289 (2008) - [c31]Thilo Pionteck, Carsten Albrecht, Roman Koch, Torben Brix, Erik Maehle:
Design and Simulation of Runtime Reconfigurable Systems. DDECS 2008: 154-157 - [c30]Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf:
Network processors. FPL 2008: 352 - [c29]Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle:
On the design parameters of runtime reconfigurable systems. FPL 2008: 683-686 - [c28]Carsten Albrecht, Philipp Roß, Roman Koch, Thilo Pionteck, Erik Maehle:
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. PDP 2008: 200-205 - [c27]Carsten Albrecht, Roman Koch, Thilo Pionteck, Erik Maehle, Michael Werner, Rudolf Fuchsen:
WCET determination tool for embedded systems software. SimuTools 2008: 48 - 2007
- [j2]Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck:
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. 49(3): 174- (2007) - [c26]Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker:
Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS 2007: 1-8 - [c25]Thilo Pionteck:
Teaching Informatics Students the Secrets of Hardware Design. MSE 2007: 31-32 - [c24]Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle:
A Lightweight Framework for Runtime Reconfigurable System Prototyping. IEEE International Workshop on Rapid System Prototyping 2007: 61-64 - 2006
- [c23]Thilo Pionteck, Carsten Albrecht, Roman Koch:
A dynamically reconfigurable packet-switched network-on-chip. DATE 2006: 136-137 - [c22]Thilo Pionteck, Roman Koch, Carsten Albrecht:
Applying Partial Reconfiguration to Networks-On-Chips. FPL 2006: 1-6 - [c21]Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle:
An adaptive system-on-chip for network applications. IPDPS 2006 - [c20]Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck:
Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV 2006: 51-60 - 2005
- [c19]Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner:
Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. ARCS Workshops 2005: 45-51 - [c18]Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf:
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS 2005: 12-21 - [c17]Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner:
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. VLSI-SoC 2005: 283-297 - 2004
- [c16]Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Lukusa D. Kabulepa, Manfred Glesner:
Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren. ARCS Workshops 2004: 155-164 - [c15]Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan:
Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers 2004: 377-389 - [c14]Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner:
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. FPGA 2004: 258 - [c13]Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner:
A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. FPL 2004: 1090-1092 - [c12]Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner:
Design of a reconfigurable AES encryption/decryption engine for mobile terminals. ISCAS (2) 2004: 545-548 - 2003
- [j1]Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner:
On the Rapid Prototyping of Equalizers for OFDM Systems. Des. Autom. Embed. Syst. 8(4): 283-295 (2003) - [c11]Thilo Pionteck, Lukusa D. Kabulepa, Clemens Schlachta, Manfred Glesner:
Reconfiguration requirements for high speed wireless communication systems. FPT 2003: 118-125 - [c10]Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner:
The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures. IEEE International Workshop on Rapid System Prototyping 2003: 141-147 - [c9]Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner:
Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans. VLSI-SoC (Selected Papers) 2003: 149-164 - [c8]Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner:
Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. VLSI-SOC 2003: 161-166 - 2002
- [c7]Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner:
A Framework for Teaching (Re)Configurable Architectures in Student Projects. FPL 2002: 444-451 - [c6]Thilo Pionteck, N. Toender, Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella:
On the Rapid Prototyping of Equalizers for OFDM Systems. IEEE International Workshop on Rapid System Prototyping 2002: 48-52 - 2001
- [c5]Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner:
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL 2001: 584-589 - [c4]Lukusa D. Kabulepa, Tideya Kella, Thilo Pionteck, Ralf Ludewig, Jürgen Becker, J. Plechinger, Manfred Glesner:
On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems. ICECS 2001: 1069-1072 - [c3]Jürgen Becker, Thilo Pionteck, Manfred Glesner:
Adaptive Systems-on-Chip: Architectures, Technologies and Applications. SBCCI 2001: 2-7 - 2000
- [c2]Jürgen Becker, Thilo Pionteck, Manfred Glesner:
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL 2000: 312-321 - [c1]Jürgen Becker, Thilo Pionteck, Manfred Glesner:
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing. SBCCI 2000: 341-346
Coauthor Index
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