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ORCIDDavid M. Russinoff
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2020 – today
- 2023
[c10]David M. Russinoff:
A Formalization of Finite Group Theory: Part II. ACL2 2023: 16-32- [c9]David M. Russinoff:
A Formalization of Finite Group Theory: Part III. ACL2 2023: 33-49 - 2022
- [b1]David M. Russinoff:
Formal Verification of Floating-Point Hardware Design - A Mathematical Approach, Second Edition. Springer 2022, ISBN 978-3-030-87180-2, pp. 1-436 - [c8]David M. Russinoff, Javier D. Bruguera, Cuong Chau, Mayank Manjrekar, Nicholas Pfister, Harsha Valsaraju:
Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking. ARITH 2022: 120-126 - [c7]David M. Russinoff:
Properties of the Hebrew Calendar. ACL2 2022: 48-60 - [c6]David M. Russinoff:
A Formalization of Finite Group Theory. ACL2 2022: 99-115 - 2020
- [c5]David M. Russinoff:
Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2. ACL2 2020: 1-15
2010 – 2019
- 2017
- [c4]David M. Russinoff:
A Computationally Surveyable Proof of the Group Properties of an Elliptic Curve. ACL2 2017: 30-46 - 2014
- [c3]John W. O'Leary, David M. Russinoff:
Modeling Algorithms in SystemC and ACL2. ACL2 2014: 145-162 - 2013
- [j9]David M. Russinoff:
Computation and Formal Verification of SRT Quotient and Square Root Digit Selection Tables. IEEE Trans. Computers 62(5): 900-913 (2013) - 2010
- [p3]David M. Russinoff:
A Mechanically Verified Commercial SRT Divider. Design and Verification of Microprocessor Systems for High-Assurance Applications 2010: 23-63
2000 – 2009
- 2007
- [c2]David M. Russinoff:
A Mathematical Approach to RTL Verification. CAV 2007: 2 - 2000
- [c1]David M. Russinoff:
A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor. FMCAD 2000: 3-36
1990 – 1999
- 1999
- [j8]David M. Russinoff:
A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode. Formal Methods Syst. Des. 14(1): 75-125 (1999) - 1998
- [j7]David M. Russinoff:
A Mechanically Checked Proof of IEEE Compliance of the Floating Point Multiplication, Division and Square Root Algorithms of the AMD-K7™ Processor. LMS J. Comput. Math. 1: 148-200 (1998) - 1995
- [j6]David M. Russinoff:
A Formalization of a Subset of VHDL in the Boyer-Moore Logic. Formal Methods Syst. Des. 7(1/2): 7-25 (1995) - 1994
- [j5]David M. Russinoff:
A Mechanically Verified Incremental Garbage Collector. Formal Aspects Comput. 6(4): 359-390 (1994) - 1993
- [p2]David M. Russinoff:
Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits. Specification and validation methods 1993: 411-460 - 1992
- [j4]David M. Russinoff:
A Verification System for Current Programs Based on the Boyer-Moore Prover. Formal Aspects Comput. 4(6A): 597-611 (1992) - [j3]David M. Russinoff:
A Mechanical Proof of Quadratic Reciprocity. J. Autom. Reason. 8(1): 3-21 (1992) - [j2]David M. Russinoff:
A Verified Prolog Compiler for the Warren Abstract Machine. J. Log. Program. 13(4): 367-412 (1992)
1980 – 1989
- 1989
- [p1]David M. Russinoff:
Proteus: A Frame-Based Nonmonotonic Inference System. Object-Oriented Concepts, Databases, and Applications 1989: 127-150 - 1985
- [j1]David M. Russinoff:
An Experiment with the Boyer-Moore Theorem Prover: A Proof of Wilson's Theorem. J. Autom. Reason. 1(2): 121-139 (1985)
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