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2020 – today
- 2024
[j39]Agata Iesurum
, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua:
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs. IEEE J. Solid State Circuits 59(1): 294-306 (2024)- [j38]Mattia de'Michieli Vitturi, Andrea Bevilacqua, Alessandro Tadini, Augusto Neri:
ELICIPY 1.0: A Python online tool for expert elicitation. SoftwareX 25: 101641 (2024) - [j37]Luca Bellemo, Andrea Bevilacqua:
On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3715-3719 (2024) - [j36]Lorenzo Tomasin, Agata Iesurum, Andrea Gobbo, Andrea Neviani, Andrea Bevilacqua:
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4718-4722 (2024) - [j35]Andrea Bevilacqua, Andrea Mazzanti:
Analysis of CMRR in Doubly-Tuned Transformer Baluns. IEEE Trans. Circuits Syst. II Express Briefs 71(12): 4874-4878 (2024) - [c57]Luca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua:
On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting. NorCAS 2024: 1-6 - [c56]Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua:
On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers. NorCAS 2024: 1-5 - [c55]Davide Pecile, Stefan Kokorovic, Alberto Gambarucci, Andrea Bevilacqua:
On the Efficiency of Output-Matched Radiofrequency Power Amplifiers. PRIME 2024: 1-4 - [c54]Nicolò Zugno, Andrea Bevilacqua:
Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology. PRIME 2024: 1-4 - 2023
- [j34]Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58(3): 634-646 (2023) - [j33]Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua:
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 607-617 (2023) - [c53]Nicolò Zugno, Francesco Brandonisio, Thomas Niederfriniger, Andrea Bevilacqua:
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies. PRIME 2023: 129-132 - [c52]Lorenzo Tomasin, Andrea Bevilacqua:
A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem. PRIME 2023: 325-328 - 2022
- [j32]Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua:
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications. IEEE J. Solid State Circuits 57(7): 1968-1981 (2022) - [j31]Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua:
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise. IEEE J. Solid State Circuits 57(9): 2802-2811 (2022) - [j30]Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57(12): 3538-3551 (2022) - [c51]Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC 2022: 1-2 - [c50]Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua:
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS. ESSCIRC 2022: 385-388 - [c49]Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC 2022: 1-3 - 2021
- [j29]Andrea Bevilacqua, Andrea Mazzanti:
Doubly-Tuned Transformer Networks: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 550-555 (2021) - [c48]Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua:
A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS. ESSCIRC 2021: 283-286 - [c47]Andrea Bevilacqua, Salvatore Levantino, Hua Wang:
Session 20 Overview: High-Performance VCOs Rf Subcommittee. ISSCC 2021: 292-293 - 2020
- [j28]Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua:
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects. IEEE J. Solid State Circuits 55(7): 1842-1853 (2020) - [j27]Simone Veni, Pietro Andreani, Michele Caruso, Marc Tiebout, Andrea Bevilacqua:
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO. IEEE J. Solid State Circuits 55(9): 2345-2355 (2020) - [c46]Gianluca Marin, Kyrylo Cherniak, Volha Subotskaya, Emanuele Bodano, Christoph Sandner, Andrea Bevilacqua:
Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c45]Andrea Bilato, Vadim Issakov, Andrea Bevilacqua:
A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS. BCICTS 2019: 1-4 - [c44]Simone Veni, Michele Caruso, Marc Tiebout, Andrea Bevilacqua:
A 17 GHz All-npn Push-Pull Class-C VCO. BCICTS 2019: 1-4 - [c43]Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Roberto Nonis, Andrea Bevilacqua:
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion. ESSCIRC 2019: 45-48 - [c42]Matteo Bassi, Giovanni Boi, Fabio Padovan, Jonas Fritzin, Stefano Di Martino, Daniel Knauder, Andrea Bevilacqua:
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS. ESSCIRC 2019: 107-110 - [c41]Alberto Gatti, Giorgio Spiazzi, Andrea Gerosa, Andrea Neviani, Andrea Bevilacqua:
A 130-nm CMOS Dual Input-Polarity DC-DC Converter for Low-Power Applications. ESSCIRC 2019: 211-214 - [c40]Gianluca Marin, Kyrylo Cherniak, Volha Subotskaya, Emanuele Bodano, Christoph Sandner, Andrea Bevilacqua:
Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters. ICECS 2019: 522-525 - [c39]Andrea Gerosa, Andrea Bevilacqua, Giorgio Spiazzi:
A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology. ISCAS 2019: 1-5 - 2018
- [j26]Andrea Bevilacqua, Shidhartha Das, Pieter Harpe:
Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 53(7): 1876-1877 (2018) - [j25]Federico Pepe, Andrea Bevilacqua, Pietro Andreani:
On the Remarkable Performance of the Series-Resonance CMOS Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 531-542 (2018) - [j24]Alessandro Franceschin, Fabio Padovan, Roberto Nonis, Andrea Bevilacqua:
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 657-661 (2018) - [j23]Paolo Scaramuzza, Carlo Rubino, Michele Caruso, Marc Tiebout, Andrea Bevilacqua, Andrea Neviani:
Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3780-3789 (2018) - [j22]Andrea Mazzanti, Andrea Bevilacqua:
Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4157-4168 (2018) - [c38]Abani K. Patra, Andrea Bevilacqua, Ali Akhavan-Safaei:
Analyzing Complex Models Using Data and Statistics. ICCS (2) 2018: 724-736 - [c37]Antonio Passamani, Davide Ponton, Andreas Wolter, Gerhard Knoblinger, Andrea Bevilacqua:
A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner. ICECS 2018: 21-24 - [c36]Hyunchol Shin, Andrea Bevilacqua, Piet Wambacq:
Session 23 overview: LO generation: RF subcommittee. ISSCC 2018: 364-365 - [c35]Fabio Padovan, Fabio Quadrelli, Matteo Bassi, Marc Tiebout, Andrea Bevilacqua:
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations. ISSCC 2018: 376-378 - 2017
- [c34]Fabio Boscolo, Fabio Padovan, Fabio Quadrelli, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset. ESSCIRC 2017: 91-94 - [c33]Paolo Scaramuzza, Carlo Rubino, Marc Tiebout, Michele Caruso, Markus Ortner, Andrea Neviani, Andrea Bevilacqua:
Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems. ESSCIRC 2017: 187-190 - [c32]Antonio Passamani, Davide Ponton, Edwin Thaller, Gerhard Knoblinger, Andrea Neviani, Andrea Bevilacqua:
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE. ISSCC 2017: 232-233 - 2016
- [j21]Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation. IEEE J. Solid State Circuits 51(7): 1525-1536 (2016) - [j20]Stefano Brenna, Fabio Padovan, Andrea Neviani, Andrea Bevilacqua, Andrea Bonfanti, Andrea L. Lacaita:
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 528-532 (2016) - [c31]Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers. ESSCIRC 2016: 363-366 - 2015
- [j19]Matteo Bassi, Junlei Zhao, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto:
A 40-67 GHz Power Amplifier With 13 dBm ℙSAT and 16% PAE in 28 nm CMOS LP. IEEE J. Solid State Circuits 50(7): 1618-1628 (2015) - [j18]Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani:
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 413-422 (2015) - [j17]Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani:
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 607-615 (2015) - [j16]Andrea Mazzanti, Andrea Bevilacqua:
On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(9): 2334-2341 (2015) - [c30]Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation. ESSCIRC 2015: 56-59 - [c29]Antonio Passamani, Davide Ponton, Gerhard Knoblinger, Andrea Bevilacqua:
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs. NORCAS 2015: 1-4 - 2014
- [c28]Junlei Zhao, Matteo Bassi, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto:
A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP. ESSCIRC 2014: 179-182 - [c27]Fabio Padovan, Andrea Bevilacqua, Andrea Neviani:
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS. ESSCIRC 2014: 287-290 - [c26]Andrea Bevilacqua, Andrea Neviani:
Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications. ICECS 2014: 874-877 - 2013
- [j15]Matteo Bassi, Michele Caruso, Andrea Bevilacqua, Andrea Neviani:
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer. IEEE J. Solid State Circuits 48(7): 1741-1750 (2013) - [c25]Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani:
Wideband 2-16GHz local oscillator generation for short-range radar applications. ESSCIRC 2013: 49-52 - [c24]Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani:
A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS. ISSCC 2013: 240-241 - 2012
- [j14]Andrea Bevilacqua, Pietro Andreani:
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 59-II(1): 20-24 (2012) - [j13]Andrea Bevilacqua, Pietro Andreani:
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(5): 938-945 (2012) - [j12]Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(6): 1228-1241 (2012) - [c23]Matteo Bassi, Michele Caruso, Andrea Bevilacqua, Andrea Neviani:
A 1.75-15 GHz stepped frequency receiver for breast cancer imaging in 65 nm CMOS. ESSCIRC 2012: 353-356 - [c22]Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani:
A SiGe bipolar VCO for backhaul E-band communication systems. ESSCIRC 2012: 402-405 - [c21]Andrea Neviani, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig:
Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications. ICICDT 2012: 1-4 - 2011
- [j11]Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani:
A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μm CMOS. IEEE J. Solid State Circuits 46(7): 1636-1647 (2011) - [c20]Andrea Bevilacqua, Pietro Andreani:
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory. ISCAS 2011: 217-220 - [c19]Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints. ISCAS 2011: 2087-2090 - [c18]Andrea Bevilacqua, Pietro Andreani:
A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2. NORCHIP 2011: 1-4 - 2010
- [j10]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. IEEE J. Solid State Circuits 45(7): 1295-1304 (2010) - [c17]Andrea Bevilacqua, Leonardo Lorenzon, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. ESSCIRC 2010: 150-153 - [c16]Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani:
A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request. ESSCIRC 2010: 498-501 - [c15]Silvia Soldà, Michele Caruso, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Low-power UWB transmitter using a combined mixer and power amplifier. ISCAS 2010: 333-336 - [c14]Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani:
A digitally programmable ring oscillator in the UWB range. ISCAS 2010: 1101-1104 - [c13]Stefano Dal Toso, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks. ISCAS 2010: 1903-1906 - [c12]Matteo Camponeschi, Andrea Bevilacqua, Andrea Neviani, Pietro Andreani:
Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end. ISCAS 2010: 2063-2066
2000 – 2009
- 2009
- [j9]Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems. IEEE J. Solid State Circuits 44(2): 331-343 (2009) - [j8]Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani:
An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 1030-1040 (2009) - [c11]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. ESSCIRC 2009: 444-447 - 2008
- [j7]Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx:
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. IEEE J. Solid State Circuits 43(12): 2693-2705 (2008) - [j6]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. IEEE J. Solid State Circuits 43(12): 2844-2852 (2008) - [c10]Silvia Soldà, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Analog decoding of trellis coded modulation for multi-level flash memories. ISCAS 2008: 744-747 - [c9]Andrea Bevilacqua, Matteo Camponeschi, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
Design of broadband inductorless LNAs in ultra-scaled CMOS technologies. ISCAS 2008: 1300-1303 - [c8]Andrea Gerosa, Maurizio Dalla Costa, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani:
An energy-detector for non-coherent impulse-radio UWB receivers. ISCAS 2008: 2705-2708 - [c7]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. ISSCC 2008: 124-125 - 2007
- [j5]Andrea Bevilacqua, Federico P. Pavan, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
Transformer-Based Dual-Mode Voltage-Controlled Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 293-297 (2007) - [j4]Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani:
An Integrated Solution for Suppressing WLAN Signals in UWB Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(8): 1617-1625 (2007) - [c6]Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOS. ESSCIRC 2007: 139-142 - [c5]Andrea Bevilacqua, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
Quadrature VCOs Based on Coupled PLLs. ISCAS 2007: 2140-2143 - [c4]Andrea Bevilacqua, Alessio Vallese, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers. ISSCC 2007: 420-612 - 2006
- [j3]Andrea Gerosa, Andrea Xotta, Andrea Bevilacqua, Andrea Neviani:
An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(10): 2109-2124 (2006) - [c3]Andrea Maniero, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency. ICECS 2006: 90-93 - [c2]Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani:
A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection. ICECS 2006: 1015-1018 - [c1]Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, Andrea Xotta:
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter. ISCAS 2006 - 2005
- [j2]Andrea Bevilacqua, Francesco Svelto:
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers. IEEE Trans. Circuits Syst. II Express Briefs 52-II(3): 117-121 (2005) - 2004
- [j1]Andrea Bevilacqua, Ali M. Niknejad:
An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers. IEEE J. Solid State Circuits 39(12): 2259-2268 (2004) - 2003
- [b1]Andrea Bevilacqua:
System analysis and circuit design of CMOS integrated wireless receivers for WCDMA and UWB applications. University of Padua, Italy, 2003
Coauthor Index
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