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ORCIDJaan Raik
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- affiliation: Tallinn University of Technology, Department of Computer Systems, Estonia
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2020 – today
- 2024
[b1]Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman:
Structural Decision Diagrams in Digital Test - Theory and Applications. Springer 2024, ISBN 978-3-031-44733-4, pp. 1-572- [j27]Tara Ghasempouri
, Jaan Raik, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil:
Survey on Architectural Attacks: A Unified Classification and Attack Model. ACM Comput. Surv. 56(2): 42:1-42:32 (2024) - [j26]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. ACM Comput. Surv. 56(6): 141:1-141:39 (2024) - [c174]Andrew Roberts, Mohammad Reza Heidari Iman, Mauro Bellone, Tara Ghasempouri, Jaan Raik, Olaf Maennel, Mohammad Hamad, Sebastian Steinhorst:
ADAssure: Debugging Methodology for Autonomous Driving Control Algorithms. DATE 2024: 1-6 - [c173]Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio:
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. DDECS 2024: 19-24 - [c172]Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin:
AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. ETS 2024: 1-4 - [c171]Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. IOLTS 2024: 1-7 - [c170]Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik:
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. ISQED 2024: 1-8 - [c169]Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab:
Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS 2024: 1-2 - [c168]Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola:
Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS 2024: 1-11 - [i28]Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik:
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. CoRR abs/2401.09509 (2024) - [i27]Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin:
AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. CoRR abs/2403.02936 (2024) - [i26]Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio:
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. CoRR abs/2403.02946 (2024) - [i25]Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. CoRR abs/2405.10658 (2024) - [i24]Seyedhamidreza Mousavi, Mohammad Hasan Ahmadilivani, Jaan Raik, Maksim Jenihhin, Masoud Daneshtalab:
ProAct: Progressive Training for Hybrid Clipped Activation Function to Enhance Resilience of DNNs. CoRR abs/2406.06313 (2024) - 2023
- [j25]Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri:
An automated method for mining high-quality assertion sets. Microprocess. Microsystems 97: 104773 (2023) - [j24]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 812-825 (2023) - [c167]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. AICAS 2023: 1-5 - [c166]Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik:
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. DDECS 2023: 124-127 - [c165]Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab, Alar Kuusik:
Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks. DFT 2023: 1-4 - [c164]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment. ETS 2023: 1-6 - [c163]Lauri Vihman, Jaan Raik:
Adaptive Kalman Filter Based Data Aggregation in Fault-Resilient Underwater Sensor Networks. DSP 2023: 1-5 - [c162]Iman Dadras, Sakineh Seydi, Mohammad Hasan Ahmadilivani, Jaan Raik, Mostafa E. Salehi:
Fully-Fusible Convolutional Neural Networks for End-to-End Fused Architecture with FPGA Implementation. ICECS 2023: 1-5 - [c161]Hardi Selg, Maksim Jenihhin, Peeter Ellervee, Jaan Raik:
ML-Based Online Design Error Localization for RISC-V Implementations. IOLTS 2023: 1-7 - [c160]Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper:
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. ISQED 2023: 1-8 - [c159]Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri:
Special Session: Approximation and Fault Resiliency of DNN Accelerators. VTS 2023: 1-10 - [e6]Maksim Jenihhin, Hana Kubátová, Nele Metens, Jaan Raik, Foisal Ahmed, Jan Belohoubek:
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023. IEEE 2023, ISBN 979-8-3503-3277-3 [contents] - [i23]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
Hybrid Protection of Digital FIR Filters. CoRR abs/2301.11115 (2023) - [i22]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessment. CoRR abs/2303.06931 (2023) - [i21]Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper:
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. CoRR abs/2303.08226 (2023) - [i20]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. CoRR abs/2305.05750 (2023) - [i19]Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik:
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. CoRR abs/2305.19733 (2023) - [i18]Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri:
Special Session: Approximation and Fault Resiliency of DNN Accelerators. CoRR abs/2306.04645 (2023) - [i17]Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. CoRR abs/2306.09973 (2023) - 2022
- [j23]Felipe Almeida, Malik Imran, Jaan Raik, Samuel Pagliarini:
Ransomware Attack as Hardware Trojan: A Feasibility and Demonstration Study. IEEE Access 10: 44827-44839 (2022) - [c158]Mohammad Reza Heidari Iman, Jaan Raik, Gert Jervan, Tara Ghasempouri:
IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets. DSD 2022: 671-678 - [c157]Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI 2022: 32-37 - [c156]Iman Dadras, Mohammad Hasan Ahmadilivani, Saoni Banerji, Jaan Raik, Alvo Aabloo:
An Efficient Analog Convolutional Neural Network Hardware Accelerator Enabled by a Novel Memoryless Architecture for Insect-Sized Robots. MOCAST 2022: 1-6 - [i16]Tara Ghasempouri, Jaan Raik, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil:
Survey on Architectural Attacks: A Unified Classification and Attack Model. CoRR abs/2208.14194 (2022) - 2021
- [j22]Lauri Vihman, Maarja Kruusmaa, Jaan Raik:
Systematic Review of Fault Tolerant Techniques in Underwater Sensor Networks. Sensors 21(9): 3264 (2021) - [c155]Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini:
Side-Channel Attacks on Triple Modular Redundancy Schemes. ATS 2021: 79-84 - [c154]Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini:
Design Space Exploration of SABER in 65nm ASIC. ASHES@CCS 2021: 85-90 - [c153]Madis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein:
Triple Fixed-Point MAC Unit for Deep Learning. DATE 2021: 1404-1407 - [c152]Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik:
CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector. DDECS 2021: 127-132 - [c151]Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar:
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD 2021: 557-561 - [c150]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS 2021: 1-7 - [c149]Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri:
A Methodology for Automated Mining of Compact and Accurate Assertion Sets. NorCAS 2021: 1-7 - [i15]Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini:
Side-Channel Attacks on Triple Modular Redundancy Schemes. CoRR abs/2104.04334 (2021) - [i14]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
High-level Intellectual Property Obfuscation via Decoy Constants. CoRR abs/2105.06122 (2021) - [i13]Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini:
Design Space Exploration of SABER in 65nm ASIC. CoRR abs/2109.07824 (2021) - [i12]Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini:
Design Space Exploration of SABER in 65nm ASIC. IACR Cryptol. ePrint Arch. 2021: 1202 (2021) - 2020
- [j21]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. 36(1): 87-103 (2020) - [j20]Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems 77: 103117 (2020) - [c148]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE 2020: 388-393 - [c147]Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil:
A Security Verification Template to Assess Cache Architecture Vulnerabilities. DDECS 2020: 1-6 - [c146]Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik:
SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks. DSD 2020: 213-217 - [c145]Mohammad Riazati, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper:
Adjustable self-healing methodology for accelerated functions in heterogeneous systems. DSD 2020: 638-645 - [c144]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD 2020: 646-650 - [c143]Lauri Vihman, Maarja Kruusmaa, Jaan Raik:
Data-Driven Cross-Layer Fault Management Architecture for Sensor Networks. EDCC 2020: 33-40 - [c142]Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil, Behrad Niazmand, Tara Ghasempouri, Jaan Raik, Johanna Sepúlveda:
LiD-CAT: A Lightweight Detector for Cache ATtacks. ETS 2020: 1-6 - [c141]Madis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein:
An Efficient FPGA-based Architecture for Contractive Autoencoders. FCCM 2020: 230 - [c140]Ameer Shalabi, Kolin Paul, Tara Ghasempouri, Jaan Raik:
NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad. ISVLSI 2020: 54-59 - [i11]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. CoRR abs/2001.09982 (2020) - [i10]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Efficient Fault Injection based on Dynamic HDL Slicing Technique. CoRR abs/2002.00787 (2020) - [i9]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. CoRR abs/2002.11108 (2020) - [i8]Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. CoRR abs/2009.11621 (2020)
2010 – 2019
- 2019
- [j19]Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu:
Understanding multidimensional verification: Where functional meets non-functional. Microprocess. Microsystems 71 (2019) - [c139]Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. DDECS 2019: 1-4 - [c138]Jan Malburg, Karl Janson, Jaan Raik, Frank Dannemann:
Fault-Aware Performance Assessment Approach for Embedded Networks. DDECS 2019: 1-4 - [c137]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS 2019: 1-6 - [c136]Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi:
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS 2019: 1-6 - [c135]Tara Ghasempouri, Alessandro Danese, Graziano Pravadelli, Nicola Bombieri, Jaan Raik:
RTL Assertion Mining with Automated RTL-to-TLM Abstraction. FDL 2019: 1-8 - [c134]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Efficient Fault Injection based on Dynamic HDL Slicing Technique. IOLTS 2019: 52-53 - [c133]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. IOLTS 2019: 239-242 - [c132]Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran:
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS 2019: 299-304 - [c131]Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu:
IEEE European Test Symposium (ETS). ITC 2019: 1-4 - [c130]Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui:
Software-Based Mitigation for Memory Address Decoder Aging. LATS 2019: 1-6 - [c129]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. LATS 2019: 1-6 - [c128]Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer:
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. NORCAS 2019: 1-7 - [c127]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) 2019: 21-44 - [c126]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC 2019: 82-87 - [c125]Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik:
Engineering of an Effective Automatic Dynamic Assertion Mining Platform. VLSI-SoC 2019: 111-116 - [i7]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. CoRR abs/1907.12325 (2019) - [i6]Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik:
Towards Multidimensional Verification: Where Functional Meets Non-Functional. CoRR abs/1908.00314 (2019) - [i5]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR abs/1908.02986 (2019) - [i4]Lauri Vihman, Maarja Kruusmaa, Jaan Raik:
Overview of Fault Tolerant Techniques in Underwater Sensor Networks. CoRR abs/1910.00889 (2019) - [i3]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR abs/1912.01561 (2019) - 2018
- [j18]Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi:
Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. 81: 252-261 (2018) - [c124]Ranganathan Hariharan, Tara Ghasempouri, Behrad Niazmand, Jaan Raik:
From RTL Liveness Assertions to Cost-Effective Hardware Checkers. DCIS 2018: 1-6 - [c123]Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin:
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. DDECS 2018: 67-72 - [c122]Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey:
Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS 2018: 147-152 - [c121]Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto García Ortiz, Rolf Drechsler:
Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling. IOLTS 2018: 247-250 - [c120]Tara Ghasempouri, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik:
An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics. ITC-Asia 2018: 61-66 - [c119]Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, Jaan Raik, Gert Jervan:
A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers. ITC-Asia 2018: 139-144 - [c118]Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies:
Timing-critical path analysis with structurally synthesized BDDs. MECO 2018: 1-6 - [c117]Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik:
Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES 2018: 305-310 - [c116]Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik:
Towards Multidimensional Verification: Where Functional Meets Non-Functional. NORCAS 2018: 1-7 - [c115]Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin:
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS 2018: 1-6 - [c114]Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik:
AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. ReCoSoC 2018: 1-6 - [c113]Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener:
Design Understanding: From Logic to Specification*. VLSI-SoC 2018: 172-175 - [c112]Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin:
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. VLSI-SoC 2018: 207-212 - 2017
- [j17]Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies:
Modeling and simulation of circuits with shared structurally synthesized BDDs. Microprocess. Microsystems 48: 56-61 (2017) - [c111]Laura Orgo, Maie Bachmann, Kaia Kalev, M. Jarvelaid, Jaan Raik, Hiie Hinrikus:
Resting EEG functional connectivity and graph theoretical measures for discrimination of depression. BHI 2017: 389-392 - [c110]Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke:
BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE 2017: 115-120 - [c109]Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein:
From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS 2017: 48-53 - [c108]Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik:
A scalable technique to identify true critical paths in sequential circuits. DDECS 2017: 152-157 - [c107]Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein:
Automated area and coverage optimization of minimal latency checkers. ETS 2017: 1-2 - [c106]Jüri Vain, Leonidas Tsiopoulos, Vyacheslav S. Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik:
Multi-Fragment Markov Model Guided Online Test Generation for MPSoC. ICTERI 2017: 594-607 - [c105]Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein:
Comprehensive performance and robustness analysis of 2D turn models for network-on-chips. ISCAS 2017: 1-4 - [c104]Stephen Adeboye Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik:
High-level test generation for processing elements in many-core systems. ReCoSoC 2017: 1-8 - [c103]Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan:
Fault-resilient NoC router with transparent resource allocation. ReCoSoC 2017: 1-8 - [e5]Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis:
VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers. IFIP Advances in Information and Communication Technology 508, Springer 2017, ISBN 978-3-319-67103-1 [contents] - 2016
- [j16]Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros:
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. 32(3): 273-289 (2016) - [c102]Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar:
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS 2016: 304-309 - [c101]Anton Karputkin, Jaan Raik:
A synthesis-agnostic behavioral fault model for high gate-level fault coverage. DATE 2016: 1124-1127 - [c100]Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao:
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL 2016: 1-8 - [c99]Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
Gate-level modelling of NBTI-induced delays under process variations. LATS 2016: 75-80 - [c98]Behrad Niazmand, Siavoosh Payandeh Azad, José Flich, Jaan Raik, Gert Jervan, Thomas Hollstein:
Logic-based implementation of fault-tolerant routing in 3D network-on-chips. NOCS 2016: 1-8 - [c97]Emmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik:
A novel random approach to diagnostic test generation. NORCAS 2016: 1-4 - [c96]Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein:
SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints. ReCoSoC 2016: 1-6 - [c95]Jaan Raik, Ian O'Connor, Thomas Hollstein, Krishnendu Chakrabarty:
Foreword. VLSI-SoC 2016: 1 - [i2]Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan, Thomas Hollstein:
Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems. CoRR abs/1601.07089 (2016) - 2015
- [j15]Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems 39(8): 909-918 (2015) - [j14]Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik:
Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems 39(8): 1130-1138 (2015) - [c94]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik:
SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. DDECS 2015: 71-74 - [c93]Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls:
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS 2015: 223-228 - [c92]Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar:
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS 2015: 251-254 - [c91]Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein:
A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. DSD 2015: 288-292 - [c90]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik:
FSMD RTL design manipulation for clock interface abstraction. ICACCI 2015: 463-468 - [c89]Jaan Raik:
Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL. HPCS 2015: 561-562 - [c88]N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls:
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS 2015: 1-6 - [c87]Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan:
A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers. NOCS 2015: 6:1-6:8 - [c86]Raimund Ubar, Lembit Jurimagi, Jaan Raik:
Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. NORCAS 2015: 1-4 - [c85]Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein:
Automated minimization of concurrent online checkers for Network-on-Chips. ReCoSoC 2015: 1-8 - [c84]Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik:
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. VLSI-SoC (Selected Papers) 2015: 23-45 - [c83]Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik:
Scalable algorithm for structural fault collapsing in digital circuits. VLSI-SoC 2015: 171-176 - [e4]Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus:
18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-6779-7 [contents] - 2014
- [j13]Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke:
Automated Design Error Localization in RTL Designs. IEEE Des. Test 31(1): 83-92 (2014) - [c82]Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik:
Critical Path Tracing Based Simulation of Transition Delay Faults. DSD 2014: 108-113 - [c81]Dmitri Mironov, Raimund Ubar, Jaan Raik:
Logic simulation and fault collapsing with shared structurally synthesized bdds. ETS 2014: 1-2 - [c80]Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar:
Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications 2014: 425-436 - [c79]Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik, Raimund Ubar:
Advanced technical education in the age of cyber physical systems. EWME 2014: 193-198 - [c78]Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti:
Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW 2014: 1-6 - 2013
- [j12]Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin:
Automated design error debug using high-level decision diagrams and mutation operators. Microprocess. Microsystems 37(4-5): 505-513 (2013) - [c77]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik:
Extensible open-source framework for translating RTL VHDL IP cores to SystemC. DDECS 2013: 112-115 - [c76]Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls:
Identifying NBTI-Critical Paths in Nanoscale Logic. DSD 2013: 136-141 - [c75]Raimund Ubar, Sergei Kostin, Jaan Raik:
Synthesis of multiple fault oriented test groups from single fault test sets. DTIS 2013: 98-103 - [c74]Urmas Repinski, Jaan Raik:
Comparison of Model-Based Error Localization algorithms for C designs. EWDTS 2013: 1-4 - [c73]Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu:
Performance analysis of cosimulating processor core in VHDL and SystemC. ICACCI 2013: 563-568 - [c72]Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
Assessment of diagnostic test for automated bug localization. LATW 2013: 1-6 - [c71]Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP 2013: 1-6 - [e3]Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka:
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6135-4 [contents] - 2012
- [j11]Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
On the Reuse of TLM Mutation Analysis at RTL. J. Electron. Test. 28(4): 435-448 (2012) - [j10]Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara:
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. 28(4): 511-521 (2012) - [c70]Jaan Raik, Vineeth Govind:
Low-area boundary BIST architecture for mesh-like network-on-chip. DDECS 2012: 95-100 - [c69]Raimund Ubar, Sergei Kostin, Jaan Raik:
Multiple stuck-at-fault detection theorem. DDECS 2012: 236-241 - [c68]Raimund Ubar, Sergei Kostin, Jaan Raik:
How to Prove that a Circuit is Fault-Free? DSD 2012: 427-430 - [c67]Jaan Raik:
FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design. ETS 2012: 1 - [c66]Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi:
Combining dynamic slicing and mutation operators for ESL correction. ETS 2012: 1-6 - [c65]Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow:
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference 2012: 260-265 - [c64]Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik:
Automated correction of design errors by edge redirection on High-Level Decision Diagrams. ISQED 2012: 686-693 - [c63]Hervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide Bertozzi:
Ultra-low latency NoC testing via pseudo-random test pattern compaction. ISSoC 2012: 1-6 - [c62]Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. LATW 2012: 1-6 - [c61]Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov:
PSL assertion checkers synthesis with ASM based HLS tool ABELITE. LATW 2012: 1-6 - [c60]Raimund Ubar, Sergei Kostin, Jaan Raik:
About robustness of test patterns regarding multiple faults. LATW 2012: 1-6 - [c59]Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke:
Localization of Bugs in Processor Designs Using zamiaCAD Framework. MTV 2012: 41-47 - [c58]Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov:
A scalable model based RTL framework zamiaCAD for static analysis. VLSI-SoC 2012: 171-176 - [e2]Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin:
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8 [contents] - 2011
- [c57]Sergei Kostin, Raimund Ubar, Jaan Raik:
Defect-oriented module-level fault diagnosis in digital circuits. DDECS 2011: 81-86 - [c56]Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik:
Probabilistic equivalence checking based on high-level decision diagrams. DDECS 2011: 423-428 - [c55]Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee:
Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. DFT 2011: 164-170 - [c54]Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara:
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS 2011: 147-152 - [c53]Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov:
Automated test bench generation for high-level synthesis flow ABELITE. EWDTS 2011: 13-16 - [c52]Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik:
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. HLDVT 2011: 83 - [c51]Valerio Guarnieri, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
Mutation analysis for SystemC designs at TLM. LATW 2011: 1-6 - [e1]Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011. IEEE Computer Society 2011, ISBN 978-1-4244-9755-3 [contents] - 2010
- [c50]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Parallel X-fault simulation with critical path tracing technique. DATE 2010: 879-884 - [c49]Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko:
Constraint-based test pattern generation at the Register-Transfer Level. DDECS 2010: 352-357 - [c48]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA 2010: 14-19 - [c47]Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD 2010: 658-663 - [c46]Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova:
An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS 2010: 13-16 - [c45]Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman:
Fault collapsing with linear complexity in digital circuits. ISCAS 2010: 653-656 - [c44]Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman:
Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED 2010: 250-257 - [c43]Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe Di Guglielmo, Franco Fummi:
Mutation analysis with high-level decision diagrams. LATW 2010: 1-6 - [i1]Yuriy A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raimund Ubar, Jaan Raik:
Evolutionary Approach to Test Generation for Functional BIST. CoRR abs/1008.0063 (2010)
2000 – 2009
- 2009
- [j9]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar:
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electron. Test. 25(6): 289-300 (2009) - [j8]Jaan Raik, Vineeth Govind, Raimund Ubar:
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Comput. Digit. Tech. 3(5): 476-486 (2009) - [c42]Raimund Ubar, Sergei Kostin, Jaan Raik:
Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. DSD 2009: 229-232 - [c41]Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman:
Structurally synthesized multiple input BDDs for simulation of digital circuits. ICECS 2009: 451-454 - [c40]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar:
High-Level Decision Diagrams based coverage metrics for verification and test. LATW 2009: 1-6 - [c39]Raimund Ubar, Sergei Kostin, Jaan Raik:
Investigations of the diagnosibility of digital networks with BIST. LATW 2009: 1-6 - [c38]Raimund Ubar, Artur Jutman, Jaan Raik, Sergei Kostin, Heinz-Dietrich Wuttke:
Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. MSE 2009: 12-15 - 2008
- [j7]Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin:
Mixed hierarchical-functional fault models for targeting sequential cores. J. Syst. Archit. 54(3-4): 465-477 (2008) - [j6]Raimund Ubar, Sergei Kostin, Jaan Raik:
Embedded fault diagnosis in digital systems with BIST. Microprocess. Microsystems 32(5-6): 279-287 (2008) - [c37]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672 - [c36]Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko:
Untestable Fault Identification in Sequential Circuits Using Model-Checking. ATS 2008: 21-26 - [c35]Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee:
Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206 - [c34]Eero Ivask, Jaan Raik, Raimund Ubar:
Web-Based Framework for Parallel Distributed Test. DDECS 2008: 271-274 - [c33]Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee:
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227 - [c32]Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz:
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD 2008: 729-734 - [c31]Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar:
Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. ETS 2008: 61-68 - [c30]Artur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar:
Reseeding using compaction of pre-generated LFSR sub-sequences. ICECS 2008: 1290-1295 - [c29]Eero Ivask, Jaan Raik, Raimund Ubar:
Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. IDC 2008: 127-136 - 2007
- [j5]Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar:
FPGA-based fault emulation of synchronous sequential circuits. IET Comput. Digit. Tech. 1(2): 70-76 (2007) - [c28]Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski:
Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40 - [c27]Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen:
Fault Diagnosis in Integrated Circuits with BIST. DSD 2007: 604-610 - [c26]Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus:
Hierarchical Identification of Untestable Faults in Sequential Circuits. DSD 2007: 668-671 - [c25]Jaan Raik, Raimund Ubar, Vineeth Govind:
Test Configurations for Diagnosing Faulty Links in NoC Switches. ETS 2007: 29-34 - [c24]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ETS 2007: 131-136 - 2006
- [c23]Jaan Raik, Vineeth Govind, Raimund Ubar:
An External Test Approach for Network-on-a-Chip Switches. ATS 2006: 437-442 - [c22]Jaan Raik, Raimund Ubar, Taavi Viilukas:
High-Level Decision Diagram based Fault Models for Targeting FSMs. DSD 2006: 353-358 - [c21]Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar:
Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. LATW 2006: 97-102 - 2005
- [j4]Jaan Raik, Tanel Nõmmeots, Raimund Ubar:
A New Testability Calculation Method to Guide RTL Test Generation. J. Electron. Test. 21(1): 71-82 (2005) - [c20]Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar:
Improved Fault Emulation for Synchronous Sequential Circuits. DSD 2005: 72-78 - [c19]Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz:
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD 2005: 79-82 - [c18]Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov:
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD 2005: 412-419 - [c17]Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman:
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344 - [c16]Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz:
DOT: new deterministic defect-oriented ATPG tool. ETS 2005: 96-101 - 2004
- [c15]Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe:
Evaluating Fault Emulation on FPGA. FPL 2004: 354-363 - [c14]Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider:
Web-Based Environment for Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks 2004: 435-442 - 2003
- [c13]Andrei Mekler, Jaan Raik:
Multiple-objective backtrace for solving test generation constraints. SoC 2003: 123-126 - [p1]Raimund Ubar, Jaan Raik:
Testing Strategies for Networks on Chip. Networks on Chip 2003: 131-152 - 2002
- [j3]T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar:
Hierarchical test generation for combinational circuits with real defects coverage. Microelectron. Reliab. 42(7): 1141-1149 (2002) - [c12]André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová:
Internet-Based Collaborative Test Generation with MOSCITO. DATE 2002: 221-226 - [c11]Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik:
Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA 2002: 86-91 - [c10]Jaan Raik, Artur Jutman, Raimund Ubar:
Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods. ICECS 2002: 445-448 - 2001
- [j2]Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar:
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectron. Reliab. 41(12): 2023-2040 (2001) - [c9]Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar:
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED 2001: 365-371 - 2000
- [j1]Jaan Raik, Raimund Ubar:
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. Electron. Test. 16(3): 213-226 (2000) - [c8]Adam Morawiec, Raimund Ubar, Jaan Raik:
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. DATE 2000: 743 - [c7]Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar:
Hierarchical defect-oriented fault simulation for digital circuits. ETW 2000: 69-74 - [c6]Raimund Ubar, Jaan Raik, Adam Morawiec:
Back-tracing and event-driven techniques in high-level simulation with decision diagrams. ISCAS 2000: 208-211 - [c5]Raimund Ubar, Jaan Raik:
Efficient Hierarchical Approach to Test Generation for Digital Systems. ISQED 2000: 189-196
1990 – 1999
- 1999
- [c4]Raimund Ubar, Jaan Raik, Adam Morawiec:
Cycle-based Simulation with Decision Diagrams. DATE 1999: 454-458 - [c3]Jaan Raik, Raimund Ubar:
Sequential Circuit Test Generation Using Decision Diagram Models. DATE 1999: 736-740 - [c2]Jaan Raik, Raimund Ubar:
High-level path activation technique to speed up sequential circuit test generation. ETW 1999: 84-89 - 1997
- [c1]Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217
Coauthor Index
Letícia Maria Veiras Bolzani
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
[b1] [j26] [c173] [c172] [c171] [c170] [c169] [c168] [i28] [i27] [i26] [i25] [i24] [j25] [c167] [c166] [c164] [c161] [c160] [c159] [e6] [i22] [i21] [i20] [i19] [i18] [i17] [c157] [c151] [c149] [j21] [j20] [c148] [c144] [i11] [i10] [i9] [i8] [j19] [c139] [c137] [c136] [c134] [c133] [c132] [c130] [c129] [c128] [c127] [c126] [i7] [i6] [i5] [i3] [j18] [c123] [c122] [c118] [c116] [c115] [c112] [c110] [c108] [c106] [j16] [c102] [c100] [c99] [c94] [c93] [c90] [c88] [j13] [c80] [c78] [j12] [c77] [c76] [c73] [c72] [j11] [j10] [c66] [c62] [c61] [c59] [c58] [e2] [c54] [c53] [c51] [c49] [c46] [c43] [j9] [c40] [j7] [c35] [c33] [c32] [c31] [c28]
Stephen Adeboye Oyeniran
aka: Adeboye Stephen Oyeniran
aka: Adeboye Stephen Oyeniran
Samuel Nascimento Pagliarini
aka: Samuel Pagliarini
aka: Samuel Pagliarini
[b1] [c157] [c151] [j21] [j20] [c144] [i8] [c139] [c137] [c132] [c129] [c127] [c126] [i7] [i5] [j18] [c118] [c117] [c115] [j17] [c109] [c108] [c104] [j16] [c102] [c99] [c97] [j15] [j14] [c93] [c92] [c86] [c84] [c83] [j13] [c82] [c81] [c80] [c79] [c78] [j12] [c76] [c75] [c72] [c71] [j11] [j10] [c69] [c68] [c66] [c64] [c62] [c60] [e2] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [i1] [j9] [j8] [c42] [c41] [c40] [c39] [c38] [j7] [j6] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [j5] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j4] [c20] [c19] [c18] [c17] [c16] [c14] [p1] [j3] [c12] [c11] [c10] [j2] [c9] [j1] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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