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ORCIDDaisuke Miyashita
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2020 – today
- 2024
[c21]Shinichi Sasaki, Yuta Aiba, Yusuke Komano, Takahiko Iizuka, Motohiko Fujimatsu, Atsushi Kawasumi, Daisuke Miyashita, Jun Deguchi, Takashi Maeda, Shinji Miyano, Tooru Maruyama:
Mitigation of Accuracy Degradation in 3D Flash Memory Based Approximate Nearest Neighbor Search with Binary Tree Balanced Soft Clustering for Retrieval-Augmented AI. NewCAS 2024: 238-242- [i7]Kento Tatsuno, Daisuke Miyashita, Taiga Ikeda, Kiyoshi Ishiyama, Kazunari Sumiyoshi, Jun Deguchi:
AiSAQ: All-in-Storage ANNS with Product Quantization for DRAM-free Information Retrieval. CoRR abs/2404.06004 (2024) - [i6]Kengo Nakata, Daisuke Miyashita, Youyang Ng, Yasuto Hoshi, Jun Deguchi:
Rethinking Sparse Lexical Representations for Image Retrieval in the Age of Rising Multi-Modal Large Language Models. CoRR abs/2408.16296 (2024) - 2023
- [c20]Yasuto Hoshi, Daisuke Miyashita, Youyang Ng
, Kento Tatsuno, Yasuhiro Morioka, Osamu Torii, Jun Deguchi:
RaLLe: A Framework for Developing and Evaluating Retrieval-Augmented Large Language Models. EMNLP (Demos) 2023: 52-69 - [i5]Yasuto Hoshi, Daisuke Miyashita, Yasuhiro Morioka, Youyang Ng, Osamu Torii, Jun Deguchi:
Can a Frozen Pretrained Language Model be used for Zero-shot Neural Retrieval on Entity-centric Questions? CoRR abs/2303.05153 (2023) - [i4]Youyang Ng, Daisuke Miyashita, Yasuto Hoshi, Yasuhiro Morioka, Osamu Torii, Tomoya Kodama, Jun Deguchi:
SimplyRetrieve: A Private and Lightweight Retrieval-Centric Generative AI Tool. CoRR abs/2308.03983 (2023) - [i3]Yasuto Hoshi, Daisuke Miyashita, Youyang Ng, Kento Tatsuno, Yasuhiro Morioka, Osamu Torii, Jun Deguchi:
RaLLe: A Framework for Developing and Evaluating Retrieval-Augmented Large Language Models. CoRR abs/2308.10633 (2023) - 2022
- [c19]Kengo Nakata, Youyang Ng, Daisuke Miyashita, Asuka Maki, Yu-Chieh Lin, Jun Deguchi:
Revisiting a kNN-Based Image Classification System with High-Capacity Storage. ECCV (37) 2022: 457-474 - [i2]Kengo Nakata, Youyang Ng, Daisuke Miyashita, Asuka Maki, Yu-Chieh Lin, Jun Deguchi:
Revisiting a kNN-based Image Classification System with High-capacity Storage. CoRR abs/2204.01186 (2022) - 2021
- [c18]Kengo Nakata, Daisuke Miyashita, Asuka Maki, Fumihiko Tachibana, Shinichi Sasaki, Jun Deguchi, Ryuichi Fujimoto:
Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN. AICAS 2021: 1-4 - [c17]Kengo Nakata, Daisuke Miyashita, Jun Deguchi, Ryuichi Fujimoto:
Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization. ISCAS 2021: 1-5 - 2020
- [j9]Asuka Maki, Daisuke Miyashita, Shinichi Sasaki, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi, Ryuichi Fujimoto:
Weight Compression MAC Accelerator for Effective Inference of Deep Learning. IEICE Trans. Electron. 103-C(10): 514-523 (2020)
2010 – 2019
- 2019
- [j8]Yuta Tsubouchi, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi:
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. IEEE J. Solid State Circuits 54(4): 1086-1095 (2019) - [c16]Shinichi Sasaki, Asuka Maki, Daisuke Miyashita, Jun Deguchi:
Post Training Weight Compression with Distribution-based Filter-wise Quantization Step. COOL CHIPS 2019: 1-3 - [c15]Kengo Nakata, Asuka Maki, Daisuke Miyashita, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi:
Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision. ISCAS 2019: 1 - 2018
- [c14]Asuka Maki, Daisuke Miyashita, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi:
FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision. A-SSCC 2018: 47-50 - [c13]Yuta Tsubouchi, Daisuke Miyashita, Yuji Satoh, Takashi Toi, Fumihiko Tachibana, Makoto Morimoto, Junji Wadatsumi, Jun Deguchi:
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems. VLSI Circuits 2018: 149-150 - 2017
- [j7]Daisuke Miyashita, Shouhei Kousai, Tomoya Suzuki, Jun Deguchi:
A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing. IEEE J. Solid State Circuits 52(10): 2679-2689 (2017) - [c12]Edward H. Lee, Daisuke Miyashita, Elaina Chai, Boris Murmann, S. Simon Wong:
LogNet: Energy-efficient neural networks using logarithmic computation. ICASSP 2017: 5900-5904 - 2016
- [c11]Daisuke Miyashita, Shouhei Kousai, Tomoya Suzuki, Jun Deguchi:
Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology. A-SSCC 2016: 25-28 - [i1]Daisuke Miyashita, Edward H. Lee, Boris Murmann:
Convolutional Neural Networks using Logarithmic Data Representation. CoRR abs/1603.01025 (2016) - 2015
- [c10]Boris Murmann, Daniel Bankman, Elaina Chai, Daisuke Miyashita, Lita Yang:
Mixed-signal circuits for embedded machine-learning applications. ACSSC 2015: 1341-1345 - 2014
- [j6]Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa:
An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. IEEE J. Solid State Circuits 49(1): 73-83 (2014) - [c9]Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki:
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. ISSCC 2014: 330-331 - [c8]Kenichi Agawa, Ichiro Seto, Akihiko Happoya, Yoshihiro Iida, Yusuke Imaizumi, Motochika Okano, Daigo Suzuki, Yuichi Sato, Masaomi Iwanaga, Kazumi Sato, Satoshi Arai, Noriaki Uchida, Koji Ryugo, Daisuke Miyashita, Ryuichi Fujimoto, Yasuo Unekawa:
3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver. RWS 2014: 76-78 - 2013
- [j5]Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Ichiro Seto, Ryuichi Fujimoto, Yasuo Unekawa:
A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJetTM SoC in 65 nm CMOS. IEICE Trans. Electron. 96-C(6): 783-789 (2013) - [c7]Yusuke Niki, Daisuke Miyashita, Hiroyuki Kobayashi, Shouhei Kousai:
A supply-noise-rejection technique in ADPLL with noise-cancelling current source. ESSCIRC 2013: 45-48 - [c6]Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa:
A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. ISSCC 2013: 420-421 - 2012
- [j4]Daisuke Miyashita, Hiroyuki Kobayashi, Jun Deguchi, Shouhei Kousai, Mototsugu Hamada, Ryuichi Fujimoto:
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. IEICE Trans. Electron. 95-C(6): 1008-1016 (2012) - [c5]Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa:
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. VLSIC 2012: 74-75 - 2011
- [j3]Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Rui Ito, Takahiro Sekiguchi, Mototsugu Hamada, Kenichi Okada:
A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 592-602 (2011) - 2010
- [j2]Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada:
A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS. IEEE J. Solid State Circuits 45(12): 2774-2784 (2010) - [c4]Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada:
A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS. ISSCC 2010: 456-457
2000 – 2009
- 2009
- [c3]Jun Deguchi, Daisuke Miyashita, Mototsugu Hamada:
A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner. ISSCC 2009: 224-225 - 2008
- [c2]Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Asuka Maki, Takahiro Sekiguchi, Rui Ito, Mototsugu Hamada:
A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier. ISSCC 2008: 214-215 - 2006
- [j1]Xueliang Song, Naoki Futakuchi, Daisuke Miyashita, Foo Cheong Yit, Yoshiaki Nakano:
Monolithically Integrated Mach-Zehnder Interferometer All-Optical Switches by Selective Area MOVPE. IEICE Trans. Electron. 89-C(7): 1068-1079 (2006) - 2005
- [c1]Daisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada:
A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations. CICC 2005: 583-586
Coauthor Index
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