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ORCIDRoberto Perez-Andrade
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2010 – 2019
- 2015
[j6]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido:
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. Microprocess. Microsystems 39(7): 576-588 (2015)- 2013
- [j5]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
On an external memory scheme for processor arrays. IEICE Electron. Express 10(14): 20130324 (2013) - [c7]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
Processor arrays generation for matrix algorithms used in embedded platforms. ReConFig 2013: 1-6 - [c6]Juan M. Campos, René Cumplido, Claudia Feregrino Uribe, Roberto Perez-Andrade:
A parallelization methodology for reconfigurable systems applied to edge detection. ReCoSoC 2013: 1-7 - 2012
- [j4]Fernando Martin del Campo, Alicia Morales-Reyes
, Roberto Perez-Andrade, René Cumplido, Aldo G. Orozco-Lugo, Claudia Feregrino:
A multi-cycle fixed point square root module for FPGAs. IEICE Electron. Express 9(11): 971-977 (2012) - 2011
- [c5]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. IPDPS Workshops 2011: 330-333 - [c4]Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade:
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig 2011: 392-397 - 2010
- [j3]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. Digit. Signal Process. 20(6): 1733-1747 (2010) - [i1]René Cumplido, Juan M. Campos, Claudia Feregrino Uribe, Jose Roberto Perez-Andrade:
Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [j2]Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo:
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. Int. J. Reconfigurable Comput. 2009: 912301:1-912301:10 (2009) - [j1]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile linear insertion sorter based on an FIFO scheme. Microelectron. J. 40(12): 1705-1713 (2009) - 2008
- [c3]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. FPL 2008: 467-470 - [c2]Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe:
A Versatile Linear Insertion Sorter Based on a FIFO Scheme. ISVLSI 2008: 357-362 - [c1]Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo:
Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. ReConFig 2008: 355-360
Coauthor Index
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