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ORCIDHeinrich Meyr
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- affiliation: RWTH Aachen University, Germany
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2020 – today
- 2020
[c140]Peng Huang, Heinrich Meyr, Meik Dörpinghaus, Gerhard P. Fettweis:
Observability Analysis of Flight State Estimation for UAVs and Experimental Validation. ICRA 2020: 4659-4665
2010 – 2019
- 2018
- [i9]Meik Dörpinghaus, Izaak Neri, Édgar Roldán, Heinrich Meyr, Frank Jülicher:
Testing Optimality of Sequential Decision-Making. CoRR abs/1801.01574 (2018) - 2017
- [j73]Dan Zhang
, Heinrich Meyr:
On the Performance Gap Between ML and Iterative Decoding of Finite-Length Turbo-Coded BICM in MIMO Systems. IEEE Trans. Commun. 65(8): 3201-3213 (2017) - [c139]Meik Dorpinghaus, Édgar Roldán, Izaak Neri, Heinrich Meyr, Frank Jülicher:
An information theoretic analysis of sequential decision-making. ISIT 2017: 3050-3054 - 2015
- [c138]I-Wei Lai, Chia-Han Lee, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh:
Channel-aware local search (CA-LS) for iterative MIMO detection. PIMRC 2015: 731-736 - [i8]Meik Dörpinghaus, Édgar Roldán, Izaak Neri, Heinrich Meyr, Frank Jülicher:
An Information Theoretic Analysis of Sequential Decision-Making. CoRR abs/1510.08952 (2015) - 2014
- [j72]Meik Dörpinghaus, Günther Koliander, Giuseppe Durisi, Erwin Riegler, Heinrich Meyr:
Oversampling Increases the Pre-Log of Noncoherent Rayleigh Fading Channels. IEEE Trans. Inf. Theory 60(9): 5673-5681 (2014) - [i7]Meik Dörpinghaus, Günther Koliander, Giuseppe Durisi, Erwin Riegler, Heinrich Meyr:
Oversampling Increases the Pre-Log of Noncoherent Fading Channels. CoRR abs/1405.0370 (2014) - 2013
- [j71]Meik Dorpinghaus, Heinrich Meyr, Rudolf Mathar:
On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels With Gaussian Inputs. IEEE Trans. Inf. Theory 59(4): 2208-2220 (2013) - 2012
- [j70]I-Wei Lai, Chien-Yi Wang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr:
Asymptotic Coded BER Analysis for MIMO BICM-ID with Quantized Extrinsic LLR. IEEE Trans. Commun. 60(10): 2820-2828 (2012) - [j69]Meik Dorpinghaus, Adrian Ispas, Heinrich Meyr:
On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels. IEEE Trans. Inf. Theory 58(5): 2963-2982 (2012) - [c137]Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Burg:
A 2.78 mm2 65 nm CMOS gigabit MIMO iterative detection and decoding receiver. ESSCIRC 2012: 65-68 - [c136]Dan Zhang, Gaojian Wang, Gerd Ascheid, Heinrich Meyr:
Searching for optimal scheduling of MIMO doubly iterative receivers: An ant colony optimization-based method. GLOBECOM 2012: 4658-4664 - [c135]Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout:
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach. INA-OCMC@HiPEAC 2012: 39-42 - [c134]Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. ICSAMOS 2012: 278-285 - 2011
- [j68]Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A retargetable framework for compiler/architecture co-development. Des. Autom. Embed. Syst. 15(3-4): 311-342 (2011) - [j67]Frank Kienle, Norbert Wehn, Heinrich Meyr:
On Complexity, Energy- and Implementation-Efficiency of Channel Decoders. IEEE Trans. Commun. 59(12): 3301-3310 (2011) - [j66]I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh:
Efficient Channel-Adaptive MIMO Detection Using Just-Acceptable Error Rate. IEEE Trans. Wirel. Commun. 10(1): 73-83 (2011) - [c133]Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Peter Burg:
A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder. A-SSCC 2011: 297-300 - [c132]I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh:
Asymptotic BER Analysis for MIMO-BICM with MMSE Detection and Channel Estimation. ICC 2011: 1-5 - [c131]Meik Dorpinghaus, Adrian Ispas, Heinrich Meyr:
Achievable rate with receivers using iterative channel estimation in stationary fading channels. ISWCS 2011: 517-521 - [i6]Meik Dörpinghaus, Adrian Ispas, Heinrich Meyr:
On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels. CoRR abs/1102.3852 (2011) - [i5]Meik Dörpinghaus, Heinrich Meyr:
On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels with Gaussian Inputs. CoRR abs/1103.0326 (2011) - 2010
- [j65]David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Automatic Generation of Memory Interfaces for ASIPs. Int. J. Embed. Real Time Commun. Syst. 1(3): 1-23 (2010) - [j64]Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Analytical and Simulation-based Design Space Exploration of Software Defined Radios. Int. J. Parallel Program. 38(3-4): 303-321 (2010) - [j63]Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 706-710 (2010) - [j62]Lars Schmitt, Heinrich Meyr, Dan Zhang:
Systematic Design of Iterative ML Receivers for Flat Fading Channels. IEEE Trans. Commun. 58(7): 1897-1901 (2010) - [j61]Lars Schmitt, Heinrich Meyr:
A Systematic Framework for Iterative Maximum Likelihood Receiver Design. IEEE Trans. Commun. 58(7): 2035-2045 (2010) - [c130]Dan Zhang, Konstantinos Nikitopoulos, I-Wei Lai, Gerd Ascheid, Heinrich Meyr:
Iterative channel estimation control for MIMO-OFDM Systems. CISS 2010: 1-6 - [c129]Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. DATE 2010: 753-758 - [c128]Chien-Yi Wang, I-Wei Lai, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr:
BER analysis for MIMO BICM-ID assuming finite precision of extrinsic LLR. ISITA 2010: 129-134 - [c127]Meik Dorpinghaus, Heinrich Meyr, Gerd Ascheid:
The achievable rate of stationary rayleigh flat-fading channels with IID input symbols. ISITA 2010: 812-817 - [c126]Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout:
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. ISVLSI (Selected papers) 2010: 65-79 - [c125]Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout:
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. ISVLSI 2010: 494-499 - [i4]Frank Kienle, Norbert Wehn, Heinrich Meyr:
On Complexity, Energy- and Implementation-Efficiency of Channel Decoders. CoRR abs/1003.3792 (2010)
2000 – 2009
- 2009
- [j60]Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Integrated verification approach during ADL-driven processor design. Microelectron. J. 40(7): 1111-1123 (2009) - [j59]Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A SIMD optimization framework for retargetable compilers. ACM Trans. Archit. Code Optim. 6(1): 2:1-2:27 (2009) - [c124]Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A high-level virtual platform for early MPSoC software development. CODES+ISSS 2009: 11-20 - [c123]Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS 2009: 305-314 - [c122]I-Wei Lai, Chun-Hao Liao, Ernst Martin Witte, David Kammler, Filippo Borlenghi, Konstantinos Nikitopoulos, Venkatesh Ramakrishnan, Dan Zhang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr:
Searching in the Delta Lattice: An Efficient MIMO Detection for Iterative Receivers. GLOBECOM 2009: 1-6 - [c121]David Kammler, Bastian Bauwens, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Anupam Chattopadhyay:
Automatic generation of memory interfaces. SoC 2009: 77-82 - [c120]Venkatesh Ramakrishnan, Joschka zur Jacobsmuehlen, I-Wei Lai, Torsten Kempf, Marc Adrat, Gerd Ascheid, Markus Antweiler, Heinrich Meyr:
Efficient implementations from libraries: Analyzing the influence of configuration parameters on key performance properties. PIMRC 2009: 873-877 - [c119]Chun-Hao Liao, I-Wei Lai, Konstantinos Nikitopoulos, Filippo Borlenghi, David Kammler, Ernst Martin Witte, Dan Zhang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr:
Combining orthogonalized partial metrics: Efficient enumeration for soft-input sphere decoder. PIMRC 2009: 1287-1291 - [c118]Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). SAMOS 2009: 204-214 - [c117]David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. SSIRI 2009: 309-314 - [c116]Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design 2009: 281-286 - [c115]I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh:
Low-Complexity Channel-Adaptive MIMO Detection with Just-Acceptable Error Rate. VTC Spring 2009 - [i3]Venkatesh Ramakrishnan, Ernst Martin Witte, Torsten Kempf, David Kammler, Gerd Ascheid, Heinrich Meyr, Marc Adrat, Markus Antweiler:
Efficient And Portable SDR Waveform Development: The Nucleus Concept. CoRR abs/0906.3313 (2009) - [i2]Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding. CoRR abs/0910.3427 (2009) - [i1]David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr:
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptol. ePrint Arch. 2009: 56 (2009) - 2008
- [j58]Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr:
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. Int. J. Embed. Syst. 3(3): 109-118 (2008) - [j57]Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr:
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. Int. J. Embed. Syst. 3(3): 150-159 (2008) - [j56]Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Power-efficient Instruction Encoding Optimization for Various Architecture Classes. J. Comput. 3(3): 25-38 (2008) - [j55]Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embed. Comput. Syst. 7(4): 40:1-40:31 (2008) - [j54]Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid:
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1281-1294 (2008) - [j53]Susanne Godtmann, I-Wei Lai, Gerd Ascheid, Tzi-Dar Chiueh, Heinrich Meyr:
Tight Approximation of the Bit Error Rate for BICM(-ID) Assuming Imperfect CSI. IEEE Trans. Wirel. Commun. 7(11-2): 4468-4473 (2008) - [c114]Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Multiprocessor performance estimation using hybrid simulation. DAC 2008: 325-330 - [c113]Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda:
MAPS: an integrated framework for MPSoC application parallelization. DAC 2008: 754-759 - [c112]Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE 2008: 1334-1339 - [c111]Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh:
Retargetable Code Optimization for Predicated Execution. DATE 2008: 1492-1497 - [c110]I-Wei Lai, Susanne Godtmann, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr:
Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. ICC 2008: 1238-1242 - [c109]Meik Dörpinghaus, Gerd Ascheid, Heinrich Meyr, Rudolf Mathar:
Optimal PSK signaling over stationary Rayleigh fading channels. ISIT 2008: 126-130 - [c108]Markus Jordan, Martin Senst, Gerd Ascheid, Heinrich Meyr:
Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. VTC Spring 2008: 275-279 - 2007
- [b4]Oliver Schliebusch, Heinrich Meyr, Rainer Leupers:
Optimized ASIP synthesis from architecture description language models. RWTH Aachen University, Germany, Kluwer 2007, ISBN 978-1-4020-5685-7, pp. I-XIV, 1-193 - [j52]Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embed. Comput. Syst. 6(2): 12 (2007) - [c107]Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A fast and generic hybrid simulation approach using C virtual machine. CASES 2007: 3-12 - [c106]Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
HySim: a fast simulation framework for embedded software development. CODES+ISSS 2007: 75-80 - [c105]Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr:
A code-generator generator for multi-output instructions. CODES+ISSS 2007: 131-136 - [c104]Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Design space exploration of partially re-configurable embedded processors. DATE 2007: 319-324 - [c103]Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE 2007: 1349-1354 - [c102]Martin Senst, Markus Jordan, Meik Dorpinghaus, Michael Farber, Gerd Ascheid, Heinrich Meyr:
Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. GLOBECOM 2007: 3812-3816 - [c101]Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD 2007: 166-171 - [c100]Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping 2007: 189-194 - [c99]Markus Jordan, Gerd Ascheid, Heinrich Meyr:
Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. VTC Spring 2007: 1652-1656 - [c98]Susanne Godtmann, André Pollok, Niels Hadaschik, Gerd Ascheid, Heinrich Meyr:
On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. VTC Spring 2007: 1723-1726 - [c97]Markus Jordan, Lars Schmitt, Gerd Ascheid, Heinrich Meyr:
Prediction of Downlink SNR for Opportunistic Beamforming. WCNC 2007: 2211-2215 - 2006
- [b3]Tim Kogel, Rainer Leupers, Heinrich Meyr:
Integrated system-level modeling of network-on-chip enabled multi-processor platforms. RWTH Aachen University, Germany, Kluwer 2006, ISBN 978-1-4020-4825-8, pp. I-XIV, 1-199 - [j51]Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. J. VLSI Signal Process. 43(2-3): 235-246 (2006) - [c96]Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren:
Retargetable code optimization with SIMD instructions. CODES+ISSS 2006: 148-153 - [c95]Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia:
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum 2006: 221-226 - [c94]Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238 - [c93]Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE 2006: 468-473 - [c92]Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Automatic ADL-based operand isolation for embedded processors. DATE 2006: 600-605 - [c91]Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE 2006: 919-924 - [c90]Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Memory Access Micro-Profiling for ASIP Design. DELTA 2006: 255-262 - [c89]Oguzhan Atak, Abdullah Atalar, Erdal Arikan, Harold Ishebabi, David Kammler, Gerd Ascheid, Heinrich Meyr, Mario Nicola, Guido Masera:
Design of Application Specific Processors for the Cached FFT Algorithm. ICASSP (3) 2006: 1028-1031 - [c88]Meik Dörpinghaus, Lars Schmitt, Ingo Viering, Axel Klein, Joachim Schmid, Gerd Ascheid, Heinrich Meyr:
Enhanced Predictive Up/Down Power Control for CDMA Systems. ICC 2006: 4327-4332 - [c87]Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, Oguzhan Atak, Abdullah Atalar, Erdal Arikan:
An efficient parallelization technique for high throughput FFT-ASIPs. ISCAS 2006 - [c86]Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson:
Flexibility and low power: a contradiction in terms? ISLPED 2006: 375 - [c85]Niels Hadaschik, Gerd Ascheid, Heinrich Meyr:
Achievable Data Rate of Wideband OFDM With Data-Aided Channel Estimation. PIMRC 2006: 1-5 - [c84]Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping 2006: 110-118 - 2005
- [c83]Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers:
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP 2005: 154-160 - [c82]Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285 - [c81]Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel:
Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254 - [c80]Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Fine-grained application source code profiling for ASIP design. DAC 2005: 329-334 - [c79]Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout:
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE 2005: 876-881 - [c78]Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun:
C Compiler Retargeting Based on Instruction Semantics Models. DATE 2005: 1150-1155 - [c77]Niels Hadaschik, Meik Dörpinghaus, Andreas Senst, Ole Harmjanz, Uwe Käufer, Gerd Ascheid, Heinrich Meyr:
Improving MIMO phase noise estimation by exploiting spatial correlations. ICASSP (3) 2005: 833-836 - [c76]Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping 2005: 165-171 - 2004
- [j50]Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr:
A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1625-1639 (2004) - [c75]Tim Kogel, Heinrich Meyr:
Heterogeneous MP-SoC: the solution to energy-efficient signal processing. DAC 2004: 686-691 - [c74]Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr:
A novel approach for flexible and consistent ADL-driven ASIP design. DAC 2004: 717-722 - [c73]Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160 - [c72]Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl:
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263 - [c71]Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren:
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE 2004: 1276-1283 - [c70]Lars Schmitt, Thomas Grundler, Christoph Schreyoegg, Gerd Ascheid, Heinrich Meyr:
Performance of initial synchronization schemes for WCDMA systems with spatio-temporal correlations. ICC 2004: 2530-2534 - [c69]Andreas Senst, Peter Schulz-Rittich, Ulrich Krause, Gerd Ascheid, Heinrich Meyr:
Random beamforming in correlated MISO channels for multiuser systems. ICC 2004: 2909-2913 - [c68]Heinrich Meyr:
Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility. SoC 2004: 1-2 - [c67]Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148 - [c66]Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452 - [c65]Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. SAMOS 2004: 463-473 - [c64]Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES 2004: 33-46 - [c63]Rudolf Mathar, Heinrich Meyr:
Stochastic modeling of the convergence behavior of concatenated codes. VTC Fall (2) 2004: 1263-1265 - 2003
- [j49]Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr:
Instruction Scheduler Generation for Retargetable Compilation. IEEE Des. Test Comput. 20(1): 34-41 (2003) - [j48]Tilman Glökler, Andreas Hoffmann, Heinrich Meyr:
Methodical Low-Power ASIP Design Space Exploration. J. VLSI Signal Process. 33(3): 229-246 (2003) - [c62]Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 - [c61]Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC 2003: 262-267 - [c60]Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl:
Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973 - [c59]Peter Schulz-Rittich, Andreas Senst, Thomas Bilke, Heinrich Meyr:
The effect of imperfect SNR knowledge on multiantenna multiuser systems with channel aware scheduling. GLOBECOM 2003: 153-157 - [c58]Michael Speth, Heinrich Meyr:
Synchronization requirements for COFDM systems with transmit diversity. GLOBECOM 2003: 1252-1256 - [c57]Lars Schmitt, Volker Simon, Thomas Grundler, Christoph Schreyoegg, Heinrich Meyr:
Initial synchronization of W-CDMA systems using a power-scaled detector with antenna diversity in frequency-selective Rayleigh fading channels. GLOBECOM 2003: 2340-2344 - [c56]Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie:
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. SCOPES 2003: 167-181 - 2002
- [b2]Andreas Hoffmann, Heinrich Meyr, Rainer Leupers:
Architecture exploration for embedded processors with LISA. Kluwer 2002, ISBN 978-1-4020-7338-0, pp. I-VIII, 1-230 - [j47]Martin Coors, Holger Keding, Olaf Lüthje, Heinrich Meyr:
Design and DSP Implementation of Fixed-Point Systems. EURASIP J. Adv. Signal Process. 2002(9): 908-925 (2002) - [c55]Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann:
A universal technique for fast and flexible instruction-set architecture simulation. DAC 2002: 22-27 - [c54]Gunnar Fock, Peter Schulz-Rittich, Andreas Schenke, Heinrich Meyr:
Low complexity high resolution subspace-based delay estimation for DS-CDMA. ICC 2002: 31-35 - [c53]Tobias Noll, Heinrich Meyr:
Designing SoC's. ISLPED 2002: 283 - [c52]Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr:
Application specific compiler/architecture codesign: a case study. LCTES-SCOPES 2002: 185-193 - [c51]Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr:
Architecture Implementation Using the Machine Description Language LISA. ASP-DAC/VLSI Design 2002: 239-244 - 2001
- [j46]Jens Baltersee, Gunnar Fock, Heinrich Meyr:
Achievable rate of MIMO channels with data-aided channel estimation and perfect interleaving. IEEE J. Sel. Areas Commun. 19(12): 2358-2368 (2001) - [j45]Gunnar Fock, Jens Baltersee, Peter Schulz-Rittich, Heinrich Meyr:
Channel tracking for RAKE receivers in closely spaced multipath environments. IEEE J. Sel. Areas Commun. 19(12): 2420-2431 (2001) - [j44]Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr:
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1338-1354 (2001) - [j43]Michael Speth, Stefan A. Fechtel, Gunnar Fock, Heinrich Meyr:
Optimum receiver design for OFDM-based broadband transmission .II. A case study. IEEE Trans. Commun. 49(4): 571-578 (2001) - [j42]Jens Baltersee, Gunnar Fock, Heinrich Meyr:
An information theoretic foundation of synchronized detection. IEEE Trans. Commun. 49(12): 2115-2123 (2001) - [c50]Holger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr:
Fast Bit-True Simulation. DAC 2001: 708-713 - [c49]A. Lock, Raul Camposano, Heinrich Meyr:
The programmable platform: does one size fit all? DATE 2001: 226-227 - [c48]Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr:
Generating production quality software development tools using a machine description language. DATE 2001: 674-678 - [c47]Andreas Hoffmann, Tim Kogel, Heinrich Meyr:
A framework for fast hardware-software co-simulation. DATE 2001: 760-765 - [c46]Martin Coors, Holger Keding, Olaf Lüthje, Heinrich Meyr:
Integer code generation for the TI TMS320C62X. ICASSP 2001: 1133-1136 - [c45]Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr:
A survey on modeling issues using the machine description language LISA. ICASSP 2001: 1137-1140 - [c44]Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr:
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. ICCAD 2001: 625-630 - [c43]Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr:
Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. ISSS 2001: 57-62 - [c42]Jens Baltersee, Gunnar Fock, Heinrich Meyr:
Achievable rate of MIMO channels with data-aided channel estimation. ITW 2001: 150-152 - 2000
- [j41]Stefan Pees, Andreas Hoffmann, Heinrich Meyr:
Retargetable compiled simulation of embedded processors using a machine description language. ACM Trans. Design Autom. Electr. Syst. 5(4): 815-834 (2000) - [c41]Jens Horstmannshoff, Heinrich Meyr:
Efficient building block based RTL code generation from synchronous data flow graphs. DAC 2000: 552-555 - [c40]Stefan Pees, Andreas Hoffmann, Heinrich Meyr:
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. DATE 2000: 669-673 - [c39]Tilman Glökler, Stefan Bitterlich, Heinrich Meyr:
DSP core verification using automatic test case generation. ICASSP 2000: 3271-3274 - [c38]Michael Speth, Alexander Jansen, Heinrich Meyr:
Iterative Multiuser Detection for Bit Interleaved Coed Modulation. ICC (2) 2000: 894-898
1990 – 1999
- 1999
- [j40]Stefan Pees, Andreas Hoffmann, Andreas Ropers, Heinrich Meyr:
Schnelle Simulation des TI-TMS320C54x DSP. Informationstechnik Tech. Inform. 41(2): 32-36 (1999) - [j39]Michael Speth, Stefan A. Fechtel, Gunnar Fock, Heinrich Meyr:
Optimum receiver design for wireless broad-band systems using OFDM. I. IEEE Trans. Commun. 47(11): 1668-1677 (1999) - [c37]Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr:
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. DAC 1999: 933-938 - [c36]Jens Horstmannshoff, Heinrich Meyr:
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. ISSS 1999: 38-43 - 1998
- [b1]Heinrich Meyr, Marc Moeneclaey, Stefan A. Fechtel:
Digital communication receivers - synchronization, channel estimation, and signal processing. Wiley series in telecommunications and signal processing, Wiley 1998, ISBN 978-0-471-50275-3, pp. I-XXV, 1-827 - [j38]Martin Vaupel, Uwe Lambrette, Herbert Dawid, Olaf J. Joeressen, Stefan Bitterlich, Heinrich Meyr, Focko Frieling, Karsten Müller, Götz Kluge:
Design Methodology for a DVB Satellite Receiver ASIC. Des. Autom. Embed. Syst. 3(4): 255-290 (1998) - [j37]Uwe Lambrette, Klaus Langhammer, Heinrich Meyr:
An Aliasing-Free Receiver with Variable Sample Rate Digital Feedback M/T NDA Timing Synchronization. Wirel. Pers. Commun. 8(2): 165-183 (1998) - [c35]Holger Keding, Markus Willems, Martin Coors, Heinrich Meyr:
FRIDGE: A Fixed-Point Design and Simulation Environment. DATE 1998: 429-435 - 1997
- [j36]Uwe Lambrette, Michael Speth, Heinrich Meyr:
OFDM burst frequency synchronization by single carrier training data. IEEE Commun. Lett. 1(2): 46-48 (1997) - [j35]Marc Moeneclaey, Heinrich Meyr:
Authors' reply [to "Comment on cycle slips in synchronizers subject to smooth narrow-band loop noise"]. IEEE Trans. Commun. 45(1): 21-22 (1997) - [j34]Vojin Zivojnovic, Steven W. K. Tjiang, Heinrich Meyr:
Compiled Simulation of Programmable DSP Architectures. J. VLSI Signal Process. 16(1): 73-80 (1997) - [c34]Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr:
Mapping multirate dataflow to complex RT level hardware models. ASAP 1997: 283- - [c33]Stefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr:
On core and more: a design perspective for systems-on-a-chip. ASAP 1997: 448-457 - [c32]Markus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr:
System Level Fixed-Point Design Based on an Interpolative Approach. DAC 1997: 293-298 - [c31]Thorsten Grötker, Rainer Schoenen, Heinrich Meyr:
PCC: a modeling technique for mixed control/data flow systems. ED&TC 1997: 482-486 - [c30]Thorsten Grötker, Rainer Schoenen, Heinrich Meyr:
Unified specification of control and data flow. ICASSP 1997: 271-274 - [c29]Markus Willems, Volker Bürsgens, Thorsten Grötker, Heinrich Meyr:
FRIDGE: an interactive code generation environment for HW/SW codesign. ICASSP 1997: 287-290 - [c28]Rainer Schoenen, Vojin Zivojnovic, Heinrich Meyr:
An upper bound of the throughput of multirate multiprocessor schedules. ICASSP 1997: 655-658 - [c27]Markus Willems, Holger Keding, Vojin Zivojnovic, Heinrich Meyr:
Modulo-addressing utilization in automatic software synthesis for digital signal processors. ICASSP 1997: 687-690 - 1996
- [j33]Klaus ten Hagen, Dirk Steinberg, Heinrich Meyr:
Codesign of a parallel architecture and an optimizing compiler backend: SIN rete processing as a case study. Des. Autom. Embed. Syst. 1(1-2): 147-176 (1996) - [j32]Herbert Dawid, Heinrich Meyr:
The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations. IEEE Trans. Computers 45(3): 307-318 (1996) - [j31]Herbert Dawid, Gerhard P. Fettweis, Heinrich Meyr:
A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 17-31 (1996) - [c26]Vojin Zivojnovic, Heinrich Meyr:
Compiled HW/SW Co-Simulation. DAC 1996: 690-695 - [c25]Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, Rainer Schoenen, Heinrich Meyr:
DSP Processor/Compiler Co-Design: A Quantitative Approach. ISSS 1996: 108- - 1995
- [j30]Heinrich Meyr, Ravi Subramanian:
Advanced digital receiver principles and technologies for PCS. IEEE Commun. Mag. 33(1): 68-78 (1995) - [j29]Olaf J. Joeressen, Heinrich Meyr:
A 40 Mb/s soft-output Viterbi decoder. IEEE J. Solid State Circuits 30(7): 812-818 (1995) - [c24]Peter Zepter, Thorsten Grötker, Heinrich Meyr:
Digital Receiver Design Using VHDL Generation from Data Flow Graphs. DAC 1995: 228-233 - [c23]Sebastian Ritz, Markus Willems, Heinrich Meyr:
Scheduling for optimum data memory compaction in block diagram oriented software synthesis. ICASSP 1995: 2651-2654 - [c22]Oliver Mauss, Matthias Pankert, Ferdinand Classen, Heinrich Meyr:
DSP-based mobile and satellite receivers, from algorithm to implementation: a design course at Aachen University of Technology. ICASSP 1995: 2881-2884 - [c21]Thorsten Grötker, Peter Zepter, Heinrich Meyr:
ADEN: an environment for digital receiver ASIC design. ICASSP 1995: 3243-3246 - [c20]Claus Schotten, Heinrich Meyr:
Test Point Insertion for an Area Efficient BIST. ITC 1995: 515-523 - [c19]Herbert Dawid, Heinrich Meyr:
Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding. PIMRC 1995: 193-197 - [c18]Olaf J. Joeressen, Heinrich Meyr:
Viterbi decoding with dual timescale traceback processing. PIMRC 1995: 213-217 - 1994
- [j28]Heinrich Meyr, Martin Oerder, Andreas Polydoros:
On sampling rate, analog prefiltering, and sufficient statistics for digital receivers. IEEE Trans. Commun. 42(12): 3208-3214 (1994) - [j27]Stefan A. Fechtel, Heinrich Meyr:
Optimal parametric feedforward estimation of frequency-selective fading radio channels. IEEE Trans. Commun. 42(234): 1639-1650 (1994) - [j26]Olaf J. Joeressen, Martin Vaupel, Heinrich Meyr:
High-speed VLSI architectures for soft-output viterbi decoding. J. VLSI Signal Process. 8(2): 169-181 (1994) - [c17]Matthias Pankert, Oliver Mauss, Sebastian Ritz, Heinrich Meyr:
Dynamic data flow and control flow in high level DSP code synthesis. ICASSP (2) 1994: 449-452 - [c16]Vojin Zivojnovic, Sebastian Ritz, Heinrich Meyr:
Retiming of DSP programs for optimum vectorization. ICASSP (2) 1994: 465-468 - [c15]Martin Vaupel, Heinrich Meyr:
High Speed FIR-Filter Architectures with Scalable Sample Rates. ISCAS 1994: 127-130 - [c14]Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele:
Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. ISCAS 1994: 129-136 - [c13]Stefan A. Fechtel, Heinrich Meyr:
Improved frame synchronization for spontaneous packet transmission over frequency-selective radio channels. PIMRC 1994: 353-357 - [c12]Uwe Lambrette, Heinrich Meyr:
A digital feedforward differential detection MSK receiver for packet-based mobile radio. VTC 1994: 282-286 - [c11]Ferdinand Classen, Heinrich Meyr:
Frequency synchronization algorithms for OFDM systems suitable for communication over frequency selective fading channels. VTC 1994: 1655-1659 - 1993
- [j25]Stefan A. Fechtel, Heinrich Meyr:
Matched Filter Bound for Trellis-Coded Transmission over Frequency-Selective Fading Channels with Diversity. Eur. Trans. Telecommun. 4(3): 343-354 (1993) - [j24]Sebastian Ritz, Matthias Pankert, Vojin Zivojnovic, Heinrich Meyr:
High-Level Software Synthesis for the Design of Communication Systems. IEEE J. Sel. Areas Commun. 11(3): 348-358 (1993) - [c10]Stefan Bitterlich, Heinrich Meyr:
Efficient scalable architectures for Viterbi decoders. ASAP 1993: 89-100 - [c9]Sebastian Ritz, Matthias Pankert, V. Zivojinovic, Heinrich Meyr:
Optimum vectorization of scalable synchronous dataflow graphs. ASAP 1993: 285-296 - [c8]Klaus ten Hagen, Heinrich Meyr:
Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project. ICCD 1993: 462-465 - [c7]Vojin Zivojnovic, Heinrich Meyr:
Design of optimum interpolation filters for digital demodulators. ISCAS 1993: 140-143 - 1992
- [c6]Herbert Dawid, Heinrich Meyr:
High speed bit-level pipelined architectures for redundant CORDIC implementation. ASAP 1992: 358-372 - [c5]Olaf J. Joeressen, Martin Vaupel, Heinrich Meyr:
High-speed VLSI architectures for soft-output Viterbi decoding. ASAP 1992: 373-384 - [c4]Sebastian Ritz, Matthias Pankert, Heinrich Meyr:
High level software synthesis for signal processing systems. ASAP 1992: 679-693 - [c3]Stefan A. Fechtel, Heinrich Meyr:
A new mobile digital radio transceiver concept using low-complexity combined equalization/trellis decoding and a near-optimal receiver sync strategy. PIMRC 1992: 382-386 - 1991
- [j23]Gerhard P. Fettweis, Heinrich Meyr:
High-speed parallel Viterbi decoding: algorithm and VLSI-architecture. IEEE Commun. Mag. 29(5): 46-55 (1991) - [j22]Abbas Aghamohammadi, Heinrich Meyr, Gerd Ascheid:
A new method for phase synchronization and automatic gain control of linearly modulated signals on frequency-flat fading channels. IEEE Trans. Commun. 39(1): 25-29 (1991) - [j21]Gerhard P. Fettweis, Heinrich Meyr:
Feedforward architectures for parallel Viterbi decoding. J. VLSI Signal Process. 3(1-2): 105-119 (1991) - 1990
- [j20]Gerhard P. Fettweis, Heinrich Meyr:
High-Rate Viterbi Processor: A Systolic Array Solution. IEEE J. Sel. Areas Commun. 8(8): 1520-1534 (1990) - [j19]Abbas Aghamohammadi, Heinrich Meyr:
On the error probability of linearly modulated signals on Rayleigh frequency-flat fading channels. IEEE Trans. Commun. 38(11): 1966-1970 (1990)
1980 – 1989
- 1989
- [j18]Reinhold Haeb, Heinrich Meyr:
A systematic approach to carrier recovery and detection of digitally phase modulated signals of fading channels. IEEE Trans. Commun. 37(7): 748-754 (1989) - [j17]Gerhard P. Fettweis, Heinrich Meyr:
Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck. IEEE Trans. Commun. 37(8): 785-790 (1989) - [j16]Gerd Ascheid, Martin Oerder, Johannes Stahl, Heinrich Meyr:
An all digital receiver architecture for bandwidth efficient transmission at high data rates. IEEE Trans. Commun. 37(8): 804-813 (1989) - [j15]Abbas Aghamohammadi, Heinrich Meyr, Gerd Ascheid:
Adaptive synchronization and channel parameter estimation using an extended Kalman filter. IEEE Trans. Commun. 37(11): 1212-1219 (1989) - 1988
- [j14]Martin Oerder, Heinrich Meyr:
Digital filter and square timing recovery. IEEE Trans. Commun. 36(5): 605-612 (1988) - [j13]Marc Moeneclaey, Stanislaw Starzak, Heinrich Meyr:
Cycle slips in synchronizers subject to smooth narrow-band loop noise. IEEE Trans. Commun. 36(7): 867-874 (1988) - [j12]Rolf Peters, Frank Blischke, Heinrich Meyr:
Transit-time estimation in turbulent flows. IEEE Trans. Acoust. Speech Signal Process. 36(1): 20-28 (1988) - [c2]Jürgen Tusch, Heinrich Meyr, Erwin A. Zurfluh:
Error handling performance of a token ring LAN. LCN 1988: 355-363 - 1987
- [j11]Heinrich Meyr, Gerhard Polzer:
A Simple Method for Evaluating the Probability Density Function of the Sample Number for the Optimum Sequential Detector. IEEE Trans. Commun. 35(1): 99-103 (1987) - 1986
- [j10]Heinrich Meyr, Luitjens Popken, Hans R. Müller:
Synchronization Failures in a Chain of PLL Synchronizers. IEEE Trans. Commun. 34(5): 436-445 (1986) - [j9]Jörg Bohmann, Heinrich Meyr:
An all-digital realization of a baseband DLL implemented as a dynamical state estimator. IEEE Trans. Acoust. Speech Signal Process. 34(3): 535-545 (1986) - 1983
- [j8]Heinz J. Keller, Heinrich Meyr, Hans R. Müller:
Transmission Design Criteria for a Synchronous Token Ring. IEEE J. Sel. Areas Commun. 1(5): 721-733 (1983) - [j7]Heinrich Meyr, Gerhard Polzer:
Performance Analysis for General PN-Spread-Spectrum Acquisition Techniques. IEEE Trans. Commun. 31(12): 1317-1319 (1983) - 1982
- [j6]Gerd Ascheid, Heinrich Meyr:
Cycle Slips in Phase-Locked Loops: A Tutorial Survey. IEEE Trans. Commun. 30(10): 2228-2241 (1982) - [c1]Heinrich Meyr, Gerhard Spies, Jörg Bohmann:
Real-time estimation of moving time delay. ICASSP 1982: 383-386 - 1980
- [j5]Heinrich Meyr, Luitjens Popken:
Phase Acquisition Statistics for Phase-Locked Loops. IEEE Trans. Commun. 28(8): 1365-1372 (1980)
1970 – 1979
- 1978
- [j4]Dietrich Ryter, Heinrich Meyr:
Theory of phase tracking systems of arbitrary order: Statistics of cycle slips and probability distribution of the state vector. IEEE Trans. Inf. Theory 24(1): 1-7 (1978) - 1977
- [j3]William C. Lindsey, Heinrich Meyr:
Complete statistical description of the phase-error process generated by correlative tracking systems. IEEE Trans. Inf. Theory 23(2): 194-202 (1977) - 1976
- [j2]Heinrich Meyr:
Delay-Lock Tracking of Stochastic Signals. IEEE Trans. Commun. 24(3): 331-339 (1976) - 1975
- [j1]Heinrich Meyr:
Nonlinear Analysis of Correlative Tracking Systems Using Renewal Process Theory. IEEE Trans. Commun. 23(2): 192-203 (1975)
Coauthor Index
[c138] [j70] [c137] [c136] [c135] [c134] [j68] [j66] [c133] [c132] [j65] [j64] [j63] [c130] [c129] [c128] [c127] [c126] [c125] [j60] [j59] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [c116] [c115] [i3] [i2] [i1] [j56] [j55] [j54] [j53] [c114] [c113] [c112] [c111] [c110] [c109] [c108] [j52] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [c97] [j51] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c89] [c88] [c87] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c73] [c72] [c71] [c70] [c69] [c67] [c66] [c65] [c64] [c62] [c56] [j22] [j16] [j15] [j6]
Meik Dörpinghaus
aka: Meik Dorpinghaus
aka: Meik Dorpinghaus
[c134] [j68] [j65] [j64] [j63] [c129] [c126] [c125] [j60] [j59] [c124] [c123] [c121] [c118] [c117] [c116] [i2] [i1] [j58] [j57] [j56] [j55] [j54] [c114] [c113] [c112] [c111] [b4] [j52] [c107] [c106] [c105] [c104] [c103] [c101] [c100] [b3] [j51] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c76] [j50] [c74] [c73] [c72] [c71] [c67] [c66] [c65] [c64] [j49] [c62] [c61] [c60] [c56] [b2] [c55] [c52]
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