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Peter Harrod
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2020 – today
- 2021
- [j8]Pete Harrod:
Memories From IBM 370 to ARM. IEEE Micro 41(6): 153-154 (2021) - [c12]Anuraag Narang, Balaji Venn, S. Saqib Khursheed, Peter Harrod:
An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults. DFT 2021: 1-6
2010 – 2019
- 2018
- [j7]Xabier Iturbe, Balaji Venu, Juergen Jagst, Emre Ozer, Peter Harrod, Chris Turner, John Penton:
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture. IEEE Des. Test 35(3): 7-14 (2018) - [c11]Emre Ozer, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton:
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. MICRO 2018: 737-748 - 2013
- [c10]Hans A. R. Manhaeve, Pete Harrod, Adit D. Singh, Chintan Patel, Ralf Arnolc, Davide Appello:
Current testing: Dead or alive? ETS 2013: 1 - 2010
- [j6]S. Saqib Khursheed, Bashir M. Al-Hashimi, Krishnendu Chakrabarty, Peter Harrod:
Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1409-1421 (2010)
2000 – 2009
- 2009
- [j5]S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Diagnosis of Multiple-Voltage Design With Bridge Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 406-416 (2009) - [j4]Urban Ingelsson, Bashir M. Al-Hashimi, S. Saqib Khursheed, Sudhakar M. Reddy, Peter Harrod:
Process Variation-Aware Test for Resistive Bridges. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1269-1274 (2009) - [c9]S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod:
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing. DATE 2009: 1349-1354 - 2008
- [j3]S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod:
Bridging Fault Test Method With Adaptive Power Management Awareness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1117-1127 (2008) - [c8]Urban Ingelsson, Bashir M. Al-Hashimi, Peter Harrod:
Variation Aware Analysis of Bridging Fault Testing. ATS 2008: 206-211 - [c7]S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Bridge Defect Diagnosis for Multiple-Voltage Design. ETS 2008: 99-104 - [c6]Ashish Darbari, Bashir M. Al-Hashimi, Peter Harrod, Daryl Bradley:
A New Approach for Transient Fault Injection Using Symbolic Simulation. IOLTS 2008: 93-98 - 2007
- [c5]Urban Ingelsson, Paul M. Rosinger, S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod:
Resistive Bridging Faults DFT with Adaptive Power Management Awareness. ATS 2007: 101-106 - 2006
- [c4]Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod:
Dynamic Voltage Scaling Aware Delay Fault Testing. ETS 2006: 15-20 - 2003
- [c3]Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod:
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. ITC 2003: 998-1007 - 2000
- [c2]Andrew Burdass, Gary Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York:
Microprocessor cores. ETW 2000: 17-22
1990 – 1999
- 1999
- [j2]Robin Saxby, Peter Harrod:
Test in the Emerging Intellectual Property Business. IEEE Des. Test Comput. 16(1): 16-18 (1999) - [c1]Peter Harrod:
Testing reusable IP-a case study. ITC 1999: 493-498 - 1993
- [j1]Peter Harrod:
Boundary-scan design for cost-sensitive applications. Microprocess. Microsystems 17(5): 277-280 (1993)
Coauthor Index
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