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ORCIDHon Nin Cheung
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2000 – 2009
- 2001
[c9]Li-Minn Ang
, Hon Nin Cheung:
Hardware implementation of the depth first search bit stream SPIHT system. ISCAS (4) 2001: 518-521- 2000
- [c8]Hon Nin Cheung, Li-Minn Ang, Kamran Eshraghian:
Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm. ACAC 2000: 3-8 - [c7]Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian:
A dataflow-oriented VLSI architecture for a modified SPIHT algorithm using depth-first search bit stream processing. ISCAS 2000: 291-294
1990 – 1999
- 1999
- [c6]Maolin Tang, Kamran Eshraghian, Hon Nin Cheung:
An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing. ASP-DAC 1999: 149-152 - [c5]Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian:
VLSI decoder architecture for embedded zerotree wavelet algorithm. ISCAS (1) 1999: 141-144 - [c4]Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian:
EZW algorithm using depth-first representation of the wavelet zerotree. ISSPA 1999: 75-78 - [c3]Hon Nin Cheung, Geoff Alagoda, Kamran Eshraghian, Li-Minn Ang:
Smart pixel VLSI architecture for embedded zerotree wavelet coding. ISSPA 1999: 693-696 - [c2]Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian:
Robust image compression using the depth-first search on the wavelet zerotree. ISSPA 1999: 797-800 - 1995
- [c1]Li-Minn Ang, Hon Nin Cheung:
Counterpropagation network and time-frequency shift-tolerant preprocessing for phoneme recognition. ICNN 1995: 2037-2040
Coauthor Index
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