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2020 – today
- 2023
[c18]Xin Su, Phillip Howard, Nagib Hakim, Steven Bethard:
Fusing Temporal Graphs into Transformers for Time-Sensitive Question Answering. EMNLP (Findings) 2023: 948-966- [i4]Gadi Singer, Joscha Bach, Tetiana Grinberg, Nagib Hakim, Phillip Howard, Vasudev Lal, Zev Rivlin:
Thrill-K Architecture: Towards a Solution to the Problem of Knowledge Based Understanding. CoRR abs/2303.12084 (2023) - [i3]Xin Su, Phillip Howard, Nagib Hakim, Steven Bethard:
Fusing Temporal Graphs into Transformers for Time-Sensitive Question Answering. CoRR abs/2310.19292 (2023) - 2022
- [c17]Costas Mavromatis, Prasanna Lakkur Subramanyam
, Vassilis N. Ioannidis, Adesoji Adeshina, Phillip Ryan Howard, Tetiana Grinberg, Nagib Hakim, George Karypis:
TempoQR: Temporal Question Reasoning over Knowledge Graphs. AAAI 2022: 5825-5833 - [c16]Gadi Singer, Joscha Bach, Tetiana Grinberg, Nagib Hakim, Phillip Ryan Howard, Vasudev Lal, Zev Rivlin:
Thrill-K Architecture: Towards a Solution to the Problem of Knowledge Based Understanding. AGI 2022: 404-412 - 2021
- [i2]Saurav Sahay, Eda Okur, Nagib Hakim, Lama Nachman:
Semi-supervised Interactive Intent Labeling. CoRR abs/2104.13406 (2021) - [i1]Costas Mavromatis, Prasanna Lakkur Subramanyam, Vassilis N. Ioannidis, Soji Adeshina, Phillip Ryan Howard, Tetiana Grinberg, Nagib Hakim, George Karypis:
TempoQR: Temporal Question Reasoning over Knowledge Graphs. CoRR abs/2112.05785 (2021) - 2020
- [j5]Francisco E. Rangel-Patino, Andres Viveros-Wacher, José Ernesto Rayas-Sánchez, Ismael Duron-Rosales, Edgar-Andrei Vega-Ochoa, Nagib Hakim, Enrique Lopez-Miralrio:
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. IEEE Trans. Emerg. Top. Comput. 8(2): 453-463 (2020)
2010 – 2019
- 2019
- [j4]Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Andres Viveros-Wacher, José Luis Chavez-Hurtado, Edgar-Andrei Vega-Ochoa, Nagib Hakim:
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 733-740 (2019) - 2018
- [c15]Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Nagib Hakim:
Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation. ITC 2018: 1-10 - [c14]Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim:
Direct optimization of a PCI express link equalization in industrial post-silicon validation. LATS 2018: 1-6 - 2016
- [j3]Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 181-190 (2016) - 2014
- [j2]David Lin, Ted Hong, Yanjing Li, Eswaran S, Sharad Kumar, Farzan Fallah, Nagib Hakim, Donald S. Gardner, Subhasish Mitra:
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1573-1590 (2014) - 2013
- [j1]Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1369-1380 (2013) - [c13]David Lin, Ted Hong, Yanjing Li, Farzan Fallah, Donald S. Gardner, Nagib Hakim, Subhasish Mitra:
Overcoming post-silicon validation challenges through quick error detection (QED). DATE 2013: 320-325 - [c12]Nagib Hakim, Charles Meissner:
Innovative practices session 1C: Post-silicon validation. VTS 2013: 1-2 - 2012
- [c11]Subhasish Mitra, David Lin, Nagib Hakim, Donald S. Gardner:
Bug localization techniques for effective post-silicon validation. ASP-DAC 2012: 291 - [c10]Nagib Hakim, A. Bhaduri, K. Donepudi, S. Bodapati:
A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation. CICC 2012: 1-5 - [c9]David Lin, Ted Hong, Farzan Fallah, Nagib Hakim, Subhasish Mitra:
Quick detection of difficult bugs for effective post-silicon validation. DAC 2012: 561-566 - 2011
- [c8]Rui Zheng, Jounghyuk Suh, Cheng Xu, Nagib Hakim, Bertan Bakkaloglu, Yu Cao:
Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability. DAC 2011: 322-327 - 2010
- [c7]Jagannath Keshava, Nagib Hakim, Chinna Prudvi:
Post-silicon validation challenges: how EDA and academia can help. DAC 2010: 3-7 - [c6]Ted Hong, Yanjing Li, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, Subhasish Mitra:
QED: Quick Error Detection tests for effective post-silicon validation. ITC 2010: 154-163
2000 – 2009
- 2008
- [c5]Pongstorn Maidee, Nagib Hakim, Kia Bazargan:
FPGA family composition and effects of specialized blocks. FPL 2008: 101-106 - 2005
- [c4]Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail:
Statistical static timing analysis: how simple can we get? DAC 2005: 652-657 - [c3]Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De:
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED 2005: 26-29 - 2004
- [c2]Sani R. Nassif, Duane S. Boning, Nagib Hakim:
The care and feeding of your statistical static timer. ICCAD 2004: 138-139 - [c1]Nagib Hakim:
Coping with Uncertainty. ISQED 2004: 9
Coauthor Index
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last updated on 2024-08-05 20:22 CEST by the dblp team
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