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ORCIDBernhard Wess
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2000 – 2009
- 2006
[j3]Markus Rupp, Bernhard Wess, Shuvra S. Bhattacharyya
:
Design Methods for DSP Systems. EURASIP J. Adv. Signal Process. 2006 (2006)- 2005
- [c12]Thomas Zeitlhofer, Bernhard Wess:
Integrated assignment of registers and functional units for heterogeneous vliw-architectures. SoCC 2005: 119-124 - 2004
- [c11]Bernhard Wess, Thomas Zeitlhofer:
Optimum address pointer assignment for digital signal processors. ICASSP (5) 2004: 121-124 - [c10]Thomas Zeitlhofer, Bernhard Wess:
A comparison of graph coloring heuristics for register allocation based on coalescing in interval graphs. ISCAS (4) 2004: 529-532 - [c9]Bernhard Wess, Thomas Zeitlhofer:
On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment. SCOPES 2004: 152-166 - 2003
- [j2]Thomas Zeitlhofer, Bernhard Wess:
List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures. Signal Process. 83(7): 1411-1425 (2003) - [c8]Thomas Zeitlhofer, Bernhard Wess:
Optimum register assignment for heterogeneous register-set architectures. ISCAS (3) 2003: 252-255 - 2000
- [c7]Bernhard Wess:
Simulated evolutionary code generation for heterogeneous memory-register DSP-architectures. EUSIPCO 2000: 1-4
1990 – 1999
- 1999
- [j1]Bernhard Wess:
Minimization of Data Address Computation Overhead in DSP Programs. Des. Autom. Embed. Syst. 4(2-3): 167-185 (1999) - [c6]Thomas Zeitlhofer, Bernhard Wess:
Operation scheduling for parallel functional units using genetic algorithms. ICASSP 1999: 1997-2000 - [c5]Stefan Fröhlich, Martin Gotschlich, Udo Krebelder, Bernhard Wess:
Dynamic trellis diagrams for optimized DSP code generation. ISCAS (3) 1999: 492-495 - 1998
- [c4]Bernhard Wess, Martin Gotschlich:
Minimization of data address computation overhead in DSP programs. ICASSP 1998: 3093-3096 - 1997
- [c3]Bernhard Wess, Martin Gotschlich:
Constructing memory layouts for address generation units supporting offset 2 access. ICASSP 1997: 683-686 - [c2]Werner Kreuzer, Bernhard Wess:
Cooperative register assignment and code compaction for digital signal processors with irregular datapaths. ICASSP 1997: 691-694 - 1994
- [c1]Bernhard Wess:
Code generation based on trellis diagrams. Code Generation for Embedded Processors 1994: 188-202
Coauthor Index
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