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2010 – 2019
- 2014
[c13]Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young:
A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). FPGA 2014: 242- [c12]Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. VLSID 2014: 375-380 - 2013
- [c11]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC 2013: 350-355 - 2012
- [j2]Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Postgrid Clock Routing for High Performance Microprocessor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 255-259 (2012) - [j1]Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu:
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme. ACM Trans. Design Autom. Electr. Syst. 17(4): 50:1-50:21 (2012) - [c10]Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. ASP-DAC 2012: 511-516 - [c9]Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu:
Almost every wire is removable: A modeling and solution for removing any circuit wire. DATE 2012: 1573-1578 - [c8]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI 2012: 327-332 - 2011
- [c7]Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu:
On applying erroneous clock gating conditions to further cut down power. ASP-DAC 2011: 509-514 - [c6]Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Grid-to-ports clock routing for high performance microprocessor designs. ISPD 2011: 21-28 - 2010
- [c5]Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu:
Logic synthesis for low power using clock gating and rewiring. ACM Great Lakes Symposium on VLSI 2010: 179-184
2000 – 2009
- 2008
- [b1]Wai-Chung Tang:
Improving FPGA designs with incremental logic resynthesis and shortcut-based routing architecture. Chinese University of Hong Kong, Hong Kong, 2008 - [c4]Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu:
A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. ERSA 2008: 116-121 - 2007
- [c3]Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu:
How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs. DAC 2007: 922-927 - [c2]Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu:
Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. ISCAS 2007: 1049-1052 - 2005
- [c1]Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang:
FPGA technology mapping optimization by rewiring algorithms. ISCAS (6) 2005: 5653-5656
Coauthor Index
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